Browsing by Author "Kuo, BJ"

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Decreasing-size distributed ESD protection scheme for broad-band RF circuits
(2005-02-01)
Ker, MD
;
Kuo, BJ
;
電機學院
;
College of Electrical and Computer Engineering
The capacitive load, from the large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broad-band RF circuits due to impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme using equal four-stage ESD protection can achieve a better impedance match, but degrade the ESD performance. A new distributed ESD protection structure is proposed to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device,size, called as decreasing-size distributed electrostatic discharge (DS-DESD) protection scheme, which is beneficial to the ESD level. The new proposed DS-DESD protection scheme With a total capacitance of 200 fF from the ESD diodes has been successfully verified in a 0.25-mum CMOS process to sustain a human-body-model ESD level of greater than 8 kV.
ESD protection design for 1-to 10-GHz distributed amplifier in CMOS technology
(2005-09-01)
Ker, MD
;
Hsiao, YW
;
Kuo, BJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-mu m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 +/- l dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 +/- 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and. high ESD robustness of the DA can be successfully codesigned to meet the application specifications.
ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme
(2004)
Ker, MD
;
Kuo, BJ
;
電機學院
;
College of Electrical and Computer Engineering
The resulting capacitive load, from the large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broadband RF circuits due to the impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme using equal four-stage ESD protection can achieve a better impedance match, but degrade the D performance. A new distributed ESD protection structure is proposed in this work to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, named decreasing-size distributed ESD (DS-DESD) protection scheme, which is beneficial to the ESD level. The experimental results had shown the human-body-model (HBM) ESD robustness of up to 8kV.
Optimization of broadband RF performance and ESD robustness by pi-model distributed ESD protection scheme
(2006-02-01)
Ker, MD
;
Kuo, BJ
;
Hsiao, YW
;
電機學院
;
College of Electrical and Computer Engineering
Large electrostatic discharge (ESD) protection devices close to the I/O pins, beneficial for ESD protection, have an adverse effect on the performance of broadband radio-frequency (RF) circuits for impedance mismatch and bandwidth degradation. A new proposed ESD protection structure, pi-model distributed ESD (pi-DESD) protection circuit, composed of one pair of ESD devices near the I/O pin, the other pair close to the core circuit, and a coplanar waveguide with under-grounded shield (CPWG) connecting these two pairs, can successfully achieve both excellent ESD robustness and good broadband RF performance. Cooperating with the active power-rail ESD clamp circuit, the experimental chip in a 0.25-mu m CMOS process can sustain the human-body-model (HBM) ESD stress of 8 kV. (c) 2005 Elsevier B.V. All rights reserved.