Browsing by Author "Kuo, CW"

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0.13-mu m RF CMOS and varactors performance optimization by multiple gate layouts
(2004-12-01)
Ho, CC
;
Kuo, CW
;
Chan, Y
;
Lien, WY
;
Guo, JC
0.13-mum radio frequency (RF) CMOS devices with multifinger gate structure have been fabricated by the standard logic process, and the measured effective gate-length is 80 nm. Extensive RF characterization has been done to obtain cutoff frequency (f(T)), associated power gain cutoff frequency (f), minimum noise figure (NFmin), output power (P-out), and power added efficiency (PAE) for RF circuit design and to explore the optimized gate layout in terms of the extracted RF device parameters. Our important finding to be reported in this paper is that an optimized unit finger width (W-F) exists by trade-off among f(T), f(.max), NFmin, P-out, and PAE. Under fixed total width to achieve the same current drivability (I-ds), the smaller W-F and the larger finger number (N-F) leads to higher f(max) but lower f(T) due to trade-off between gate resistance (R-g) and parasitic gate capacitance. As for NFmin complicated by f(T) and R-g, counter-balance between parasitic gate capacitance and R-g leads to nearly constant NFmin. w.r.t. various splits of (W-F, N-F). Regarding P-out and PAE, W-F of 4 mum and NF of 18 is the optimized layout parameter, which offers the maximum P-out of around 11 dBm and PAE of 30.5% at 5.8 GHz. The performances of accumulation-mode MOS varactors with different gate layout structures are also investigated in this report. Since the same area varactors with different gate layout may result in different parasitic resistance and fringing capacitance, which will affect the capacitance tuning range and the associated Q-factor. The maximum Q-factor is about 59 of the 120 mum(2) gate area varactor, and its tuning range is from 210 IF to 1.64 pF, where the maximum C-max/C-min ratio is about 7.8.
Optimization of back side cleaning process to eliminate copper contamination
(2005)
Chou, WY
;
Tsui, BY
;
Kuo, CW
;
Kang, TK
;
電子工程學系及電子研究所
Copper (Cu) contamination at the wafer bevel, back side surface, and exclusion zone is identified step-by-step following a typical dual-damascene process. The shield ring of a physical vapor deposition system does not protect the exclusion zone and bevel efficiently. Also, Cu may dissolve and accumulate in the solvent used for post dielectric etch clean. Dissolved Cu atoms may then redeposit on the wafer surface. Furthermore, the rough back side surface traps Cu atoms easier than the smooth front side surface. If there is no SiO2 film on the back side surface, post chemical mechanical polish cleaning using dilute HF cannot remove Cu at the back side surface. An optimized single-wafer spin-etch process was proposed. An optimal etchant consisting of HF, HNO3, H2SO4, and H3PO4 with ratios 0.5 :3 :1 :0.5 showed excellent performance. Experiments demonstrated that a very short, 10 s, back side clean can totally remove Cu from back side surface, bevel, and 2 mm exclusion zone. A "wafer shift" procedure was also proposed to solve the pinmark issue near the edge pin due to etchant remnant. The optimized cleaning technique shows shorter process time and higher cleaning efficiency than those reported previously. (C) 2005 The Electrochemical Society.