Browsing by Author "Kuo, Chien-Nan"

Now showing 1 - 20 of 68

16.9-mW 33.7-dB Gain mm Wave Receiver Front-End in 65 nm CMOS
(2012)
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a low power receiver front-end design for the 77 GHz radar application. The theoretical maximum achievable gains in the LNA and the mixer are derived by using energy conservation principle. It is shown that the maximum gain can be increased by raising the impedance ratio between stages. The impedance transformation is able to provide high passive gain without any power consumption. Moreover, the quality of the passive components plays a critical role to approach the maximum gain condition. Accordingly a low power receiver front-end is designed in 65 nm CMOS. The measured results show the highest gain of 33.7 dB at 73 GHz with 3 dB bandwidth from 67 GHz to 75 GHz. The input return loss, P1dB, IIP3, and NF at IF frequency of 8 MHz, are 16.4 dB, -32 dBm, -19 dBm, and 12.2 dB, respectively. The power consumption is only 16.9 mW from a 1 V supply. To the best of our knowledge, this work shows the highest gain while consumes the lowest power as compared to the prior works.
3 similar to 11-GHz CMOS UWB LNA using dual feedback for broadband matching
(2006)
Fu, Chang-Tsung
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 1.5V, 3 similar to 11GHz CMOS UWB LNA using dual feedback loops is reported. Using shunt capacitive feedback and series transformer feedback the broadband matching condition is achieved with high flat gain. Fabricated in 0.18um CMOS process, the measurement result demonstrates power gain of 11dB and maximum NF less than 5.6 dB throughout the frequency range from 3.1 to 10.6 GHz with power consumption of 10.6 mW.
3 similar to 11-GHz CMOS UWB LNA using dual feedback for broadband matching
(2006-01-01)
Fu, Chang-Tsung
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 1.5V, 3 similar to 11GRz CMOS UWB LNA using dual feedback loops is reported. Using shunt capacitive feedback and series transformer feedback the broadband matching condition is achieved with high flat gain. Fabricated in 0.18um CMOS process, the measurement result demonstrates power gain of 11dB and maximum NF less than 5.6dB throughout the frequency range from 3.1 to 10.6 GHz with power consumption of 10.6mW.
A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique
(2011-06-01)
Li, Chun-Hsing
;
Liu, Yen-Lin
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this study, a low-power and low-voltage 5.5-GHz receiver front-end circuit is designed using a resonator coupling technique. An on-chip transformer combined with the parasitic capacitances from a low-noise amplifier (LNA), a mixer, and the transformer itself comprises two coupled resonators of the resonator coupling network (RCN). The RCN functions as a balun, and couples energy from the LNA to the mixer. Under the critical coupling condition, the RCN gives a maximal current gain at resonance frequencies, equivalent to the same level by an ideal transformer. The analysis shows that the current gain is quite tolerable to the coupling coefficient variation, an advantageous feature for on-chip transformer design. The technique is verified by the receiver front-end in 0.18-mu m CMOS technology. The RCN possess a current gain as high as 12 dB at 5.5 GHz. The measured input return loss, conversion gain, and third-order intermodulation intercept point of the entire circuit are 16 dB, 17.4 dB, and -1.5 dBm, respectively. The noise figure is 7.8 dB at the IF frequency of 1 MHz. The power consumption is only 0.33 mW from a 0.6-V supply. The required local oscillator power is only -9.5 dBm. This receiver front-end successfully demonstrates the resonator coupling technique.
A 0.75-2.67 GHz 5-bit Vector-Sum Phase Shifter
(2013)
Yan, Tzu-Chao
;
Lin, Wei-Zhen
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 5-bit active vector-sum phase shifter operated in 0.75-2.67 GHz is implemented in 0.18-mu m CMOS technology. A tunable RC quadrature all-pass filter and a resistor-string VGA are proposed for quadrature phase generation and magnitude ratio tuning, respectively. The chip size is 0.89 mm(2). The DC power consumption of core circuit is 6.39 mW from 1.8 V supply. The RMS magnitude error and RMS phase error are below 0.74 dB and 7.2 degrees.
A 1-4 GHz Frequency-to-Voltage Converter Design
(2012)
Kuan, Chih-Kuang
;
Yan, Tzu-Chao
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A broadband frequency-to-voltage converter is designed to operate at the multi-GHz frequency band. The circuit detects the input signal frequency and generates a DC output voltage correspondingly, regardless of the input power variation through a two-path signal process of frequency discrimination and signal power reference. One advantage of the design utilizing power detection makes the method feasible for very high frequency applications. The integrated design is verified in an integrated system mixed with off-the-shelf commercial components. Measurement results show a maximum output voltage RMS error of 2.1% over the input frequency from 1 GHz to 4 GHz with the input power level -30 dBm to 0 dBm.
A 1-5 GHz Frequency-to-Voltage Converter Using Limiting Amplifier
(2016)
Lin, Han-Bo
;
Yan, Tzu-Chao
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A frequency-to-voltage converter (FVC) is designed for directly converting an input radio-frequency to a dc output voltage over a wide microwave frequency range. The proposed circuit consists of a limiting amplifier (LA) for converting input frequency to correspond ac magnitude and a power detector for ac magnitude to dc voltage conversion. Consequently, the circuit converts the signal frequency of 1-5 GHz to the measured dc voltage of 0.25-1.39 V under the input power level at +5 dBm. The RMS error is below 1.37 %. Implemented in 0.18 mu m CMOS technology, the dc power consumption varies from 17.4 to 19.4 mW with 1.8 V supply voltage, depending on the input frequency. The fabricated chip occupies the size of 860 x 500 mu m(2).
A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 mu m CMOS
(2009-03-01)
Kuo, Ming-Ching
;
Kao, Shiau-Wen
;
Chen, Chih-Hung
;
Hung, Tsun-Shuen
;
Shih, Yi-Shing
A fully integrated direct-conversion tuner is implemented in 0.13 mu m CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L-bands, and occupies only 7.2 mm(2) die area.
A 1.2-V 5.2-mW 20-30-GHz Wideband Receiver Front-End in 0.18-mu m CMOS
(2012-11-01)
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-mu m CMOS technology. The experimental result shows that the -3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 mm(2).
A 1.2V Interference-Sturdiness, DC-Offset Calibrated CMOS Receiver Utilizing a Current-Mode Filter for UWB
(2008)
Shih, Horng-Yuan
;
Chen, Wei-Hsien
;
Juang, Kai-Chenug
;
Yang, Tzu-Yi
;
Kuo, Chien-Nan
An interference-sturdiness receiver with a current-mode filter for 3-5GHz UWB applications is implemented in a 1.2V 0.13 mu m CMOS process. The chip provides a maximum voltage gain of 70dB and a dynamic range of 60dB. The measured in-band OIP3 is +9.39dBm, out-of-band IIP3 -15dBm and noise figure 6.8dB in the maximum gain mode. An algorithm for the automatic digital DC offset calibration is also demonstrated.
A 1.3 GHz-5.3 GHz Wideband, High Linearity Balun Low Noise Amplifier
(2011)
Yang, Kai-Hsiang
;
Kuo, Ming-Ching
;
Yan, Tzu-Chao
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
In this work, a balun low-noise amplifier (LNA) is designed and implemented in 0.18-mu m CMOS process. The bulk cross-coupling (BCC) and capacitance cross-coupling (CCC) techniques are introduced in this LNA, which not only increase gain and linearity but also decrease noise figure. The 3 dB bandwidth extends from 1.27 GHz to 5.31 GHz. The maximum differential gain is 10.13 dB. Measured at 3 GHz, P-1dB and IIP3 are -10 dBm and 0 dBm, respectively. The LNA core circuit dissipates 7.32 mW from 1.8 V power supply.
A 11-mW Quadrature Frequency Tripler with Fundamental Cancellation
(2010)
Tsai, Chien-Chung
;
Chang, Derric
;
Chen, Huan-Sheng
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
A low-power quadrature frequency tripler is designed by using the sub-harmonic mixer configuration. The circuit is implemented in CMOS 0.180um technology. The frequency tripler consumes 11.5mW, while the output buffers consumes 43.1mW, all with supply voltage of 1.8V. The fundamental Harmonic Rejection Ratio (HRR(1)) achieves more than 35dB, and the conversion gain achieves -4.2dB at output frequency of 4.5GHz. The entire chip area occupied 1.4x1.1 mm(2).
A 147 GHz Fully Differential D-Band Amplifier Design in 65 nm CMOS
(2013)
Li, Chun-Hsing
;
Lai, Chih-Wei
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a 147 GHz D-band fully differential amplifier design in 65 nm CMOS. By using a T-network, composed of three inductors, to replace an on-chip transformer, the proposed impedance transformation network can provide an impedance transformation ratio larger than one. So the passive gain can be acquired to increase the amplifier gain. The measured results show that the amplifier can provide power gain of 7.1 dB at 147 GHz. The power consumption is 104 mW from a 2 V supply voltage.
A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS
(2019-01-01)
Sun, Wei-Che
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-nm bulk CMOS. The output stage is optimized to achieve high output power while maintaining high power added efficiency (PAE). The complete PA achieves a measured saturated output power of 22.4 dBm and the 19.1% PAE at 2.4 V supply. It has -3 dB bandwidth of 8.8 GHz.
A 2.4 to 5.4 GHz low power CMOS reconfigurable LNA for multistandard wireless receiver
(2007)
Fu, Chang-Tsung
;
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
交大名義發表
;
National Chiao Tung University
A CMOS reconfigurable LNA is reported. By combination of switched inductors and varactors it performs continuous frequency tuning from 2.4 to 5.4 GHz with 500MHz 3dB-bandwidth. Switching transistor is used to provide variable gain control over a 12dB-range. The LNA supports standards including Bluetooth, WiMAX, UWB mode-1, 802.11b/g and part of 802.11a. Fabricated in 0.13um CMOS process the LNA achieves up to 25dB power gain, 2.2dB noise figure, -1dBm IIP3 while consuming less than 5mV from 1-V power supply.
A 2.4-5.4-GHz Wide Tuning-Range CMOS Reconfigurable Low-Noise Amplifier
(2008-12-01)
Fu, Chang-Tsung
;
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
Juang, Ying-Zong
;
電子工程學系及電子研究所
A 2.4-5.4-GHz CMOS reconfigurable low-noise amplifier (LNA) is designed. It consists of two stages: a broadband input stage for a steady input matching and noise performance, and a reconfigurable band-selective stage which provides a wide-range frequency tuning from 2.4 to 5.4 GHz and a 12-dB stepped gain with linearity adjustment. The frequency tuning is conducted by a multitapped switching inductor and varactors. Careful design of the switching inductor achieves consistent performance among frequency configurations. The stepped gain and linearity adjustment are provided by a size-switchable transistor with a variable biasing. Fabricated in 0.13 mu m CMOS technology this LNA exhibits performance including up to 25 dB power gain, 2.2-3.1 dB noise figure and less than 5 mW power consumption under 1 V power supply.
A 210-GHz Amplifier in 40-nm Digital CMOS Technology
(2013-06-01)
Ko, Chun-Lin
;
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.
A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband
(2010-02-01)
Shih, Horng-Yuan
;
Kuo, Chien-Nan
;
Chen, Wei-Hsien
;
Yang, Tzu-Yi
;
Juang, Kai-Chenug
A 250 MHz analog baseband chain for Ultra-Wideband was implemented in a 1.2 V 0.13 mu m CMOS process. The chip has an active area of 0.8 mm(2). In the analog baseband, PGAs and filters are carried out by current-mode amplifiers to achieve wide bandwidth and wide dynamic range of gain, as well as low noise and high linearity. Besides, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers. A 6th-order Chebyshev low-pass filter realized in G(m)-C topology is designed in the baseband chain for channel selection. Digitally-assisted DC-offset calibration improves second-order distortion of the entire chain. The design achieves a maximum gain of 73 dB and a dynamic range of 82 dB. Measured noise figure is 14 dB, an IIP3 of -6 dBV, and IIP2 of -5 dBV at the maximum gain mode. The analog baseband chain consumes 56.4 mA under supply of 1.2 V.
A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS
(2014-12-01)
Li, Chun-Hsing
;
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm(2).
A 37.5-mW 8-dBm-EIRP 15.5 degrees-HPBW 338-GHz Terahertz Transmitter Using SoP Heterogeneous System Integration
(2015-02-01)
Li, Chun-Hsing
;
Chao, Tzu-Yuan
;
Lai, Chih-Wei
;
Chen, Wei-Cheng
;
Ko, Chun-Lin
A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 degrees. The EIRP can be further raised to 9.5 dBm as the supply V-DD is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 mm(2). All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors\' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.