Browsing by Author "Kuo, Chun-Chieh"

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93% Efficiency and 0.99 Power Factor in Pseudo-linear LED Driver
(2016-01-01)
Chiu, Shao-Wei
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Kuo, Chun-Chieh
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Chuang, Kai-Cheng
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Yang, Wen-Hau
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Chen, Ke-Horng
The proposed pseudo-linear LED driver can effectively solve the serious flicker in conventional linear LED driver (LLD). Besides, it has good electromagnetic interference (EMI) performance similar to that in conventional LLD at high AC input voltage. In the meanwhile, it has high power factor (PF) similar to boost switching regulator (SWR) LED driver at low AC input voltage. Furthermore, owing to the combination of line filter and the active full bridge rectifier, the pseudo-linear LED driver has a compact solution and high efficiency. The test chip was fabricated in 0.5 mu m 500V LDMOS process. Experimental results show 93% high efficiency, 6% total harmonic distortion (THD), and 0.99 PF at the power of 7W.
A 4.2 nW and 18 ppm/degrees C Temperature Coefficient Leakage-Based Square Root Compensation (LSRC) CMOS Voltage Reference
(2019-05-01)
Huang, Chao-Jen
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Lai, Yan-Jiun
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Yang, Yu-Jheng Ou
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Chen, Hung-Wei
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Kuo, Chun-Chieh
State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1 similar to 1.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100 similar to 300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer sigma/mu of 0.204 and a TC of 18 ppm/degrees C with a power consumption of 4.2 nW.
A 70W and 90% GaN-Based Class-E Wireless-Power-Transfer System with Automatic-Matching-Point-Search Control for Zero-Voltage Switching and Zero-Voltage-Derivative Switching
(2018-01-01)
Yeh, Che-Hao
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Lin, Yen-Ting
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Kuo, Chun-Chieh
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Huang, Chao-Jen
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Xie, Cheng-Yu
A 70W and 90% GaN-Based Class-E Wireless-Power-Transfer System with Automatic-Matching-Point-Search Control for Zero-Voltage Switching and Zero-Voltage-Derivative Switching
(2018-01-01)
Yeh, Che-Hao
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Lin, Yen-Ting
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Kuo, Chun-Chieh
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Huang, Chao-Jen
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Xie, Cheng-Yu
A 97% Maximum Efficiency Fully Automated Control Turbo Boost Topology for Battery Chargers
(2019-11-01)
Muniandi, Balakumar
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Huang, Chao-Jen
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Kuo, Chun-Chieh
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Yang, Te-Fu
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Chen, Ke-Horng
In this paper, the proposed topology of a fully automated control (FAC) battery charger that provides turbo-boost operation and fully automated detection without any feedback from the system is discussed. It uses closed-loop control for automatic system load detection and automatically adjusts the battery discharge current. The advantages include shortened battery discharge time and maximum power provided by the adapter. Therefore, the FAC technique is flexible for any load system that is limited to battery chargers with the turbo boost mode support. In addition, to avoid over discharge, a battery protection circuitry is also included. The test chip is fabricated using a 0.25- $\mu \text{m}$ CMOS process, with a maximum efficiency of 94.58 & x0025; when the charger operates in the turbo boost mode, and achieves 97 & x0025; maximum efficiency when the charger operates in buck charge mode.
A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT
(2018-01-01)
Huang, Chao-Jen
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Ma, Yao-Sheng
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Yang, Wen-Hau
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Lin, Yen-Ting
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Kuo, Chun-Chieh
this paper provides a Single-Inductor Quadruple-Input--Quadruple-Output buck-boost converter to achieve maximum tracking efficiency of 99,2% due to continuous supply in one cycle. The Maximum Power Point (MPP) tracking mode and the Harvest Energy Delivering (RED) mode harvest each energy harvesting source, deliver energy to the battery and supply it to the loading system in one cycle. Each output voltage ranges from 600mV to 2.5V and the maximum output power is up to 60mW. The peak efficiency is 91.2%.
A Single-Inductor Dual-Output Converter With the Stacked MOSFET Driving Technique for Low Quiescent Current and Cross Regulation
(2019-03-01)
Chen, Hsin
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Huang, Chao-Jen
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Kuo, Chun-Chieh
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Lin, Li-Chi
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Ma, Yu-Sheng
Stacked MOSFET structures made of low-voltage devices suffer from degraded transient response or large footprint when a capacitorless or dominant-pole compensated low-dropout (LDO) regulator biases the driver. Due to the self-stabilizing nature, the proposed stacked MOSFET driver (SMD) technology effectively drives the power stage and greatly reduces the noise at the switching nodes for low cross regulation (CR) in a single-inductor dual-output (SIDO) converter. In addition, two inherent LDO regulators in SMD technology fully regulate the dual outputs with the advantage of low quiescent current at no-load conditions. The experimental results show that the test chip fabricated under the 0.25-mu m process has low CR of 0.015 mV/mA and ultralow quiescent current of 5 mu A under no-load conditions.
A True-Random-Number-Based Pseudohysteresis Controller for Buck DC-DC Converter in High-Security Internet-of-Everything Devices
(2020-03-01)
Yang, Wen-Hau
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Chiu, Shao-Wei
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Kuo, Chun-Chieh
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Lin, Yen-Ting
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Lai, Yan-Jiun
For high-security Internet-of-Everything (IoE) devices, a true random number (TRN)-based pseudohysteresis controller (PHC) is proposed to avoid both power side-channel attack (PSCA) and power injection attack (PIA) and reduce electromagnetic interference (EMI) without degrading performance of transient response and regulation. In addition, the TRN-based PHC uses an enhanced security randomizer to correctly generate a random number (RN) independent of the input power at the PSCA and PIA and converts the RN into a hysteresis window that constitutes the true random modulation switching frequency. Therefore, the TRN-based PHC ensures proper spread spectrum and low EMI. In addition, fast transient response is maintained due to inherent hysteresis control. Experimental results show that peak EMI noise is reduced from 89.72 to 54.32dBV and meets the specification of EN 55032 Class B even under the PIA interference up to 1 V. Furthermore, in case of 0.2A-to-0.8A load step, the method achieves a recovery time of 7.3 s and an output voltage drop of 53 mV at a switching frequency of approximately 1 MHz, and the peak efficiency is 92.4.
Delay-Lock-Loop-Based Inductorless and Electrolytic Capacitorless Pseudo-Sine-Current Controller in LED Lighting Systems
(2015-12-01)
Chiu, Shao-Wei
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Kuo, Chun-Chieh
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Su, Yi-Ping
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Chen, Ke-Horng
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電控工程研究所
Light-emitting diode lighting system with the proposed pseudo-sine-current controller removes most of the external passive components, which include inductor, electrolytic capacitor, freewheel diode, blocking diode, and the bleeding circuit for Triac dimming control, for low cost and small volume. Delay-lock loop control can ensure the in-phase operation of ac input voltage and current for high power factor (PF) and low total harmonic distortion (THD). In addition, redundant power loss in Triac dimming control is eliminated to get a high efficiency of 85%. Furthermore, a high PF of 0.997 and a low THD of 7.74% are also achieved owing to in-phase line voltage and current.
Detecting Solid-State Disk Geometry for Write Pattern Optimization
(2011-01-01)
Kuo, Chun-Chieh
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Hsieh, Jen-Wei
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Chang, Li-Pin
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交大名義發表
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National Chiao Tung University
Solid-state disks use flash memory as their storage medium, and adopt a firmware layer that makes data mapping and wear leveling transparent to the hosts. Even though solid-state disks emulate a collection of logical sectors, the I/O delays of accessing all these logical sectors are not uniform because the management of flash memory is subject to many physical constraints of flash memory. This work proposes a collection of black-box tests can detect the geometry inside of a solid-state disk. The host system software can arrange data in the logical disk space according to the detected geometry information to match the host write pattern with the device characteristic for reducing the flash management overhead in solid-state disks.