Browsing by Author "Kuo, Han-Wen"

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A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-12-01)
Chiu, Shih-Wen
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Wang, Jen-Huo
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Chang, Kwuang-Han
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Chang, Ting-Hau
;
Wang, Chia-Min
Ventilator-associated pneumonia (VAP) still lacks a rapid diagnostic strategy. This study proposes installing a nose-on-a-chip at the proximal end of an expiratory circuit of a ventilator to monitor and to detect metabolite of pneumonia in the early stage. The nose-on-a-chip was designed and fabricated in a 90-nm 1P9M CMOS technology in order to downsize the gas detection system. The chip has eight on-chip sensors, an adaptive interface, a successive approximation analog-to-digital converter (SAR ADC), a learning kernel of continuous restricted Boltzmann machine (CRBM), and a RISC-core with low-voltage SRAM. The functionality of VAP identification was verified using clinical data. In total, 76 samples infected with pneumonia (19 Klebsiella, 25 Pseudomonas aeruginosa, 16 Staphylococcus aureus, and 16 Candida) and 41 uninfected samples were collected as the experimental group and the control group, respectively. The results revealed a very high VAP identification rate at 94.06% for identifying healthy and infected patients. A 100% accuracy to identify the microorganisms of Klebsiella, Pseudomonas aeruginosa, Staphylococcus aureus, and Candida from VAP infected patients was achieved. This chip only consumes 1.27 mW at a 0.5 V supply voltage. This work provides a promising solution for the long-term unresolved rapid VAP diagnostic problem.
A Java Processor IP Design for Embedded SoC
(2015-03-01)
Tsai, Chun-Jen
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Kuo, Han-Wen
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Lin, Zigang
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Guo, Zi-Jing
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Wang, Jun-Fu
In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.
A Single-Walled Carbon Nanotube Network Gas Sensing Device
(2011-08-01)
Wang, Li-Chun
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Tang, Kea-Tiong
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Teng, I-Ju
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Kuo, Cheng-Tzu
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Ho, Cheng-Long
The goal of this research was to develop a chemical gas sensing device based on single-walled carbon nanotube (SWCNT) networks. The SWCNT networks are synthesized on Al(2)O(3)-deposted SiO(2)/Si substrates with 10 nm-thick Fe as the catalyst precursor layer using microwave plasma chemical vapor deposition (MPCVD). The development of interconnected SWCNT networks can be exploited to recognize the identities of different chemical gases by the strength of their particular surface adsorptive and desorptive responses to various types of chemical vapors. The physical responses on the surface of the SWCNT networks cause superficial changes in the electric charge that can be converted into electronic signals for identification. In this study, we tested NO(2) and NH(3) vapors at ppm levels at room temperature with our self-made gas sensing device, which was able to obtain responses to sensitivity changes with a concentration of 10 ppm for NO(2) and 24 ppm for NH(3).
Stack Memory Design for a Low-cost Instruction Folding Java Processor
(2012)
Lin, Zi-Gang
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Kuo, Han-Wen
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Guo, Zi-Jing
;
Tsai, Chun-Jen
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資訊工程學系
In this paper, we propose the design of the stack memory for a low-cost Java processor that explores instruction-level parallelism. The Java virtual machine (JVM) is a stack machine where the instruction execution pipeline uses a stack to store intermediate computation results and local variables. High performance Java processors often use a large stack cache to enable parallel accesses to operands and local variables to achieve instruction-level parallelism. We propose a low-cost alternative of stack memory design that allows the Java processor to access the critical stack operands and local variables concurrently. The stack memory is constructed using seven registers and two blocks of dual-port on-chip SRAM; and is optimized for the Java instruction set architecture. When coupled with a low-cost two-way instruction folding pipeline, micro-benchmark results show that the proposed architecture can achieve up to 45.4% 2-fold instruction folding rate.