Browsing by Author "Kuo, Ming-Ching"

Now showing 1 - 13 of 13

A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 mu m CMOS
(2009-03-01)
Kuo, Ming-Ching
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Kao, Shiau-Wen
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Chen, Chih-Hung
;
Hung, Tsun-Shuen
;
Shih, Yi-Shing
A fully integrated direct-conversion tuner is implemented in 0.13 mu m CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L-bands, and occupies only 7.2 mm(2) die area.
A 1.2-V 5.2-mW 20-30-GHz Wideband Receiver Front-End in 0.18-mu m CMOS
(2012-11-01)
Li, Chun-Hsing
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Kuo, Chien-Nan
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Kuo, Ming-Ching
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-mu m CMOS technology. The experimental result shows that the -3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 mm(2).
A 1.3 GHz-5.3 GHz Wideband, High Linearity Balun Low Noise Amplifier
(2011)
Yang, Kai-Hsiang
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Kuo, Ming-Ching
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Yan, Tzu-Chao
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Kuo, Chien-Nan
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電子工程學系及電子研究所
In this work, a balun low-noise amplifier (LNA) is designed and implemented in 0.18-mu m CMOS process. The bulk cross-coupling (BCC) and capacitance cross-coupling (CCC) techniques are introduced in this LNA, which not only increase gain and linearity but also decrease noise figure. The 3 dB bandwidth extends from 1.27 GHz to 5.31 GHz. The maximum differential gain is 10.13 dB. Measured at 3 GHz, P-1dB and IIP3 are -10 dBm and 0 dBm, respectively. The LNA core circuit dissipates 7.32 mW from 1.8 V power supply.
A 210-GHz Amplifier in 40-nm Digital CMOS Technology
(2013-06-01)
Ko, Chun-Lin
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Li, Chun-Hsing
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Kuo, Chien-Nan
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Kuo, Ming-Ching
;
Chang, Da-Chiang
This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.
A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS
(2014-12-01)
Li, Chun-Hsing
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Ko, Chun-Lin
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Kuo, Chien-Nan
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Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm(2).
A 37.5-mW 8-dBm-EIRP 15.5 degrees-HPBW 338-GHz Terahertz Transmitter Using SoP Heterogeneous System Integration
(2015-02-01)
Li, Chun-Hsing
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Chao, Tzu-Yuan
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Lai, Chih-Wei
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Chen, Wei-Cheng
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Ko, Chun-Lin
A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 degrees. The EIRP can be further raised to 9.5 dBm as the supply V-DD is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 mm(2). All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors\' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.
A 8-mW 77-GHz Band CMOS LNA by Using Reduced Simultaneous Noise and Impedance Matching Technique
(2015)
Ko, Chun-Lin
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Li, Chun-Hsing
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Kuo, Chien-Nan
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Kuo, Ming-Ching
;
Chang, Da-Chiang
This paper presents analysis and design of source inductance for multistage LNA at 77-GHz band in 90 nm CMOS technology. Instead of simultaneous noise and impedance matching, the analysis shows the optimum degeneration of the single stage design for millimeter-wave frequencies. A low-power 77-GHz band LNA has been demonstrated to verify the optimization result. By using the proposed method, the LNA exhibited a low noise figure of 5.1 dB and a gain of 18.1 dB at 78.5 GHz with only 8 mW from a 1-V power supply.
A Broadband Interconnect for THz Heterogeneous System Integration
(2013)
Li, Chun-Hsing
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Wu, Jan-Jr
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Kuo, Chien-Nan
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Cheng, Yu-Ting
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Kuo, Ming-Ching
A broadband interconnect for THz heterogeneous system integration is proposed using a resonator coupling technique. Two resonators, deployed on a chip and a carrier, respectively, are coupled through the electromagnetic field to provide a low-loss interconnect in a broadband manner. Simulation results indicate an insertion loss of 0.32 dB at 170 GHz while covering 3-dB bandwidth from 100 to 344 GHz. Measurement can be conducted to verify its performance only from 140 GHz to 220 GHz, due to equipment limit. The measured minimum insertion loss is 0.47 dB at 164 GHz.
A High Q On-Chip Bondwire Transformer and Its Application to Low Power Receiver Front-End Design
(2013)
Li, Chun-Hsing
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Kuo, Chien-Nan
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Kuo, Ming-Ching
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a high Q on-chip bondwire transformer and its application to a low power receiver front-end design. The proposed bondwire transformer has the advantage of high quality factor, less sensitivity to the bonding height variation, and working as a balun to conduct single-to-differential conversion. Furthermore, the chip area under the bondwire transformer can be reused by the mixer and buffer circuits to reduce the cost. The receiver front-end is realized in 1P6M 0.18 mu m CMOS technology. The measured input return loss, the conversion gain, the noise figure, and the input third-order intercept point are 12.7 dB, 20.5 dB, 9.8 dB, and -4.0 dBm, respectively, at 2.1 GHz. The power consumption is only 1.1 mW from a 1 V supply.
A Low-Cost Broadband Bondwire Interconnect for Heterogeneous System Integration
(2013)
Li, Chun-Hsing
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Ko, Chun-Lin
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Kuo, Chien-Nan
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Kuo, Ming-Ching
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Chang, Da-Chiang
A low-cost broadband interconnect, composed of bondwires and transmission lines, is proposed for heterogeneous system integration. By designing the length and the characteristic impedance of the transmission lines, the bondwire effect can be reduced to provide an interconnect with good return loss and low insertion loss. In this work, the chip and the carrier are realized in 90-nm CMOS and GIPD process, respectively. Measured results show that the return loss and the insertion loss are better than 10 dB and 1.1 dB, respectively, from DC to 45.2 GHz.
A Low-Cost DC-to-84-GHz Broadband Bondwire Interconnect for SoP Heterogeneous System Integration
(2013-12-01)
Li, Chun-Hsing
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Ko, Chun-Lin
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Kuo, Chien-Nan
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Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-cost broadband bondwire interconnect is proposed for heterogeneous system integration. Transmission lines are incorporated with bondwires to form a two-path structure, which can effectively reduce the bondwire effect. Theoretical analysis is provided using a graphical method and it shows that the interconnect can give widest operation bandwidth from dc up to a maximum frequency f(max) if the length of the transmission lines is designed at an optimal electrical length theta(max) . In particular, theta(max) only depends on the characteristic impedance of the transmission lines. The achievable f(max) is limited by the bondwire inductance, i.e., smaller bondwire inductance is preferred to have wider operation bandwidth. An interconnect from a 0.18-mu m CMOS chip to a glass-integrated-passive-device carrier is designed to verify the proposed concept. Measured results show that the insertion loss and the return loss can be better than 3.0 and 13.4 dB, respectively, from dc to 84 GHz. The proposed interconnect shows around 3.2 times bandwidth of a single bondwire alone. To the best of authors' knowledge, this work demonstrates the bondwire interconnect with the widest operation bandwidth for heterogeneous system integration by using system-on-package reported thus far.
Constant Excess Bias Control for Single-Photon Avalanche Diode Using Real-Time Breakdown Monitoring
(2015-08-01)
Chang, Po-Hsuan
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Tsai, Chia-Ming
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Wu, Jau-Yang
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Lin, Sheng-Di
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Kuo, Ming-Ching
A monolithic constant excess bias control circuit for single-photon avalanche diode (SPAD) in standard 0.18-mu m CMOS technology is reported. The proposed real-time breakdown monitoring technique is incorporated into a passive-quenching-active-reset circuit. A sample-and-hold circuit samples the breakdown level of SPAD through well-defined sampling phase. Following the sample-and-hold circuit, the level shifter with voltage shifting defined by predetermined excess bias provides the reset voltage of SPAD. The design operates the SPAD under constant excess bias and effectively mitigates the impact of the process-voltage-temperature variation by maintaining the optimal excess bias condition.
Wideband LNA Compatible for Differential and Single-Ended Inputs
(2009-07-01)
Kuo, Ming-Ching
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Kuo, Chien-Nan
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Chueh, Tzu-Chan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter presents a wideband low-noise amplifier (LNA) that supports both differential and single-ended inputs, while providing differential output. The LNA is implemented in 0.13 mu m. CMOS technology. For sub-1 GHz wideband applications, this LNA achieves 22.5 dB voltage gain, +1 dBrn IIP3, and 2.5 dB NF in the differential receiving mode, while achieving 23 dB voltage gain, -0.5 dB m IIP3, and 2.65 dB NF in the single-ended receiving mode. The LNA core circuit draws 2.5 mA from 1.2 V supply voltage, and occupies a small chip area of 0.06 mm(2).