Browsing by Author "Kuo, Po-I"

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A Delta Sigma TDC with Sub-ps Resolution for PLL Built-in Phase Noise Measurement
(2016)
Chen, Wei-Zen
;
Kuo, Po-I
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A sub-ps Delta Sigma TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and Delta Sigma TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm(2).