Browsing by Author "Kuo, Shih-Hua"

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Random Pattern Generation for Post-Silicon Validation of DDR3 SDRAM
(2015)
Yang, Hao-Yu
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Kuo, Shih-Hua
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Huang, Tzu-Hsuan
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Chen, Chi-Hung
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Lin, Chris
Due to the demand of pursuing a main memory with larger data bandwidth, higher data density, and lower power, the specification of DRAM has been constantly evolved in the past decade. The new DRAM specifications support multiple operating modes with multiple timing settings. It then becomes computationally infeasible to exhaustively validate all the combinations of different operating modes, timing settings and address/data with pure simulation before silicon. In this paper, we propose a framework to generate proper random patterns for validating a newly designed DDR3 SDRAM based on its first silicon chips. The proposed framework needs to not only guarantee the correctness of the generated patterns according to the state diagram and timing constraints defined in the specification but also provide the flexibility of exploring various design corners for the targeted DDR3 SDRAM. We will also show some successful silicon-validation cases of applying the proposed framework to identify the design errors based on real DDR3 SDRAM products.
Statistical Techniques for Predicting System-Level Failure using Stress-Test Data
(2015)
Chen, Harry H.
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Kuo, Shih-Hua
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Tung, Jonathan
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Chao, Mango C. -T.
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電子工程學系及電子研究所
In this paper we describe a novel scheme for collecting and analyzing a chip\'s failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip\'s "analog" failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.
Testing Retention Flip-flops in Power-gated Designs
(2013)
Hsu, Hao-Wen
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Kuo, Shih-Hua
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Chang, Wen-Hsiang
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Chen, Shi-Hao
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Chang, Ming-Tung
This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V-DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-V-DD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.