Browsing by Author "Kuo, Shu-Chiao"

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A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration
(2018-02-01)
Lee, Shih-Wei
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Kuo, Shu-Chiao
;
Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.
Breakthrough in Cu to Cu Pillar-Concave Bonding on Silicon Substrate with Polymer Layer for Advanced Packaging, 3D, and Heterogeneous Integration
(2017-01-01)
Yang, Yu-Tao
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Yu, Ting-Yang
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Kuo, Shu-Chiao
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Huang, Tai-Yuan
;
Yang, Kai-Ming
In this paper, finite element method (FEM) simulations are carried out with pillar-concave structure using silicon substrate, silicon substrate with polyimide (PI) and with polybenzoxazole (PBO) for realization of Cu-Cu bonding at low temperature. Parameters of bonding temperature, pillar diameter, concave sidewall angle, and multilayer of concave structure are all considered in simulation. In addition, pillarconcave bonding is successfully demonstrated on silicon substrates with bonding temperatures ranging from 60 degrees C to 100 degrees C. Simulation and fabrication results of concept show potential impacts on current semiconductor packaging method with advantages such as high adhesive strength of polymer on various types of substrates, simplified manufacturing process, solder free interconnect and packaging process, Cu-Cu direct bonding at temperature lower than 100 degrees C, and high tolerance in surface roughness.
Electrical Testing Structure for Stacking Error Measurement in 3D Integration
(2016)
Lee, Shih-Wei
;
Kuo, Shu-Chiao
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel electrical test structure is proposed to inspect the stacking fault in 3D integration. This approach is one nondestructive analysis of the misalignment investigation. In order to determine the misalignment of wafer/chip stacking, the metal line pattern is designed to detect the direction and quantity of stacking fault. Testing circuit diagram is proposed and simulated for efficient measurement. In addition, different types of stacking fault including translation, rotation, and run out are discussed and formulated.