Browsing by Author "Kuo, Tzu-Yun"

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A 242mW, 10mm(2) 1080p H.264/AVC high profile encoder chip
(2008)
Lin, Yu-Kun
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Li, De-Wei
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Lin, Chia-Chun
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Kuo, Tzu-Yun
;
Wu, Sian-Jin
A 1080p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mu m CMOS technology with an area of 10 mm(2) and 242mW at 145MHz. Compared to the state-of-the-art design targeted at 720p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline.
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
(2008-07-01)
Lin, Yu-Kun
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Lin, Chia-Chun
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Kuo, Tzu-Yun
;
Chang, Tian-Sheuan
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電子工程學系及電子研究所
Motion estimation (ME) in high-definition H.264 video coding presents a significant design challenge for memory bandwidth, latency, and cost because of its large search range and various modes. To conquer this problem, this paper presents a low-latency and hardware-efficient ME design with three design techniques. The first technique on integer-pel ME (IME) adopts parallel instead of serial multiresolution search so that we can process 1080 p @ 60 fps videos with +/- 128 search range within just 256 cycles, 5.95-KB buffers, and 213.7K gates. The second technique on fractional-pel ME (FME) uses a single-iteration six-point search to reduce the cycle count by half with similar gate count and negligible quality loss. The third technique applies a mode-filtering approach to further reduce the bandwidth and cycles and share the buffer of IME and FME. The final ME implementation with 0.13-mu m process can support processing of 1080 p @ 60 fps with just 128.8 MHz, 282.6 K gates, and 8.54-KB buffer, which saves 60% gate count, and 68.9% SRAM buffers when compared with the previous design.
A memory bandwidth optimized interpolator for motion compensation in the H.264 video decoding
(2006)
Kuo, Tzu-Yun
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Lin, Yu-Kun
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Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The paper presents an interpolator design for motion compensation used in the H.264 video decoding. The presented design is optimized according to the available data bandwidth to avoid the idle hardware. In addition, the required memory access is further reduced by the interpolation window optimization. The implementation shows that the presented design can save about 10% of silicon area or at least seven interpolation filters than that in the previous works. Besides, 12.50% to 71.3% of cycle count of motion compensation can be reduced by the interpolator window optimization. Finally, our architecture can be easily adjusted under different memory bandwidth.
SIFME: A single iteration fractional-pel motion estimation algorithm and architecture for HDTV sized H.264 video coding
(2007)
Kuo, Tzu-Yun
;
Lin, Yu-Kun
;
Chang, Tian-Sheuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a set of fast algorithm and VLSI architecture for HDTV-sized H.264 fractional motion estimation. To solve the long computational latency in HD-sized application, we propose to use the single iteration algorithm with only six search points. This single iteration method halves the cycle count of two iteration methods in previous approaches. Moreover, we propose to use 4x4 Hadamard instead of 8x8 Hadamard as cost function for H.264 high profiles without significant video quality loss. By these techniques, the resulted architecture can save 20% of area and provide over 40% of throughput improvement than the previous work, and is able to support HDTV applications.