Browsing by Author "Kuo, Yi-Ping"

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A DUAL-EDGED TRIGGERED EXPLICIT-PULSED LEVEL CONVERTING FLIP-FLOP WITH A WIDE OPERATION RANGE
(2013-01-01)
Chen, Mei-Wei
;
Chang, Ming-Hung
;
Wu, Pei-Chen
;
Kuo, Yi-Ping
;
Yang, Chun-Lin
In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converters may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a dual-edged triggered explicitpulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate (DCVSPG) latch. The clock pulse generator has the symmetric pulse triggering time and holding period helping shorten the D-Q delay. By employed diode-connected PMOS transistors and two NMOS transistor stacked below the diode PMOS transistors, the proposed DETEP-LCFF can be operated from near-threshold region to superthreshold region. It is implemented in TSMC 65nm CMOS technology. It functions correctly across all process corners with a wide input voltage range, from 400mV to 1V. The proposed LCFF has a minimum D-Q delay of 781 ps, a setup time of 610ps, and a power dissipation of 2.3 mu W when the input voltage is OAV.
All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration for Ripple Reduction
(2015)
Kuo, Yi-Ping
;
Huang, Po-Tsang
;
Wu, Chung-Shiang
;
Liang, Yu-Jie
;
Chuang, Ching-Te
In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best ( lowest) FOM of 0.76 pA.s can be realized.
An All-Digital Power Management Unit with 90% Power Efficiency and ns-order Voltage Transition Time for DVS Operation in Low Power Sensing SoC Applications
(2015)
Wu, Chung-Shiang
;
Lin, Kai-Chun
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Kuo, Yi-Ping
;
Chen, Po-Hung
;
Chu, Yuan-Hua
A 1V similar to 1.2V battery input, 0.4V similar to 0.6V output low-power all-digital power management unit (PMU) composed of a high-efficiency digital buck converter (DBC) and a fast-transient digital low drop-out (DLDO) regulator is developed for energy-efficient SoC applications. A fully integrated 2-to-1 switchedcapacitor dc-dc converter is combined together to reduce the quiescent current of digital control circuits. The digital pulse width modulation (DPWM) with clock frequency gating further reduces the power consumption of buck converter in steady state. From experiment results, the peak power efficiency of the proposed buck converter is 90% with an output power range of 30 mu W to 3mW and the peak current efficiency of DLDO is 98.8% at 5mW. Moreover, the proposed DLDO achieves 92ns/ 130ns transition time in 60mV voltage step to dynamically scaling the voltage of supply voltage in digital circuits. This chip is designed and fabricated in 65nm CMOS process for verification.
Zika Virus NS3 Protease Pharmacophore Anchor Model and Drug Discovery
(2020-06-02)
Pathak, Nikhil
;
Kuo, Yi-Ping
;
Chang, Teng-Yuan
;
Huang, Chin-Ting
;
Hung, Hui-Chen
Zika virus (ZIKV) of the flaviviridae family, is the cause of emerging infections characterized by fever, Guillain-Barre syndrome (GBS) in adults and microcephaly in newborns. There exists an urgent unmet clinical need for anti-ZIKV drugs for the treatment of infected individuals. In the current work, we aimed at the promising virus drug target, ZIKV NS3 protease and constructed a Pharmacophore Anchor (PA) model for the active site. The PA model reveals a total of 12 anchors (E, H, V) mapped across the active site subpockets. We further identified five of these anchors to be critical core anchors (CEH1, CH3, CH7, CV1, CV3) conserved across flaviviral proteases. The ZIKV protease PA model was then applied in anchor-enhanced virtual screening yielding 14 potential antiviral candidates, which were tested by in vitro assays. We discovered FDA drugs Asunaprevir and Simeprevir to have potent anti-ZIKV activities with EC50 values 4.7 mu M and 0.4 mu M, inhibiting the viral protease with IC50 values 6.0 mu M and 2.6 mu M respectively. Additionally, the PA model anchors aided in the exploration of inhibitor binding mechanisms. In conclusion, our PA model serves as a promising guide map for ZIKV protease targeted drug discovery and the identified 'previr' FDA drugs are promising for anti-ZIKV treatments.