Browsing by Author "LI, HH"

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A NEW GATE CURRENT SIMULATION TECHNIQUE CONSIDERING SI/SIO2 INTERFACE-TRAP GENERATION
(1995-04-01)
WEN, KS
;
LI, HH
;
WU, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An efficient and accurate 2D numerical simulation technique is developed to study the hot-electron effects on short-channel n-MOSFETs. The 1D substrate injection probability used by Ning el al, has been further modified by considering the channel hot-electron-enhanced injection probability. Moreover, the hot-electron-injection-induced Si/SiO2 interface-trap generation and its effects on MOSFET drain, substrate and gate currents have also been taken into consideration. It is shown that the generated electron traps at the Si/SiO2 interface enhance both the impact ionization rate and the degradation of MOSFET characteristics but retard the injection probability of hot electrons into the gate oxide. The spatial distribution of the generated Si/SiO2 interface traps calculated by our model has been well verified by the charge pumping measurement. In addition, the simulated substrate current, gate current, and degradation of drain current are in good agreement with the experimental results of a short-channel n-MOSFET with the oxide thickness of 100 Angstrom and the effective channel length of 0.45 mu m for wide ranges of drain and gate biases.
A NOVEL EXTRACTION TECHNIQUE FOR THE EFFECTIVE CHANNEL-LENGTH OF MOSFET DEVICES
(1995-05-01)
LI, HH
;
WU, CY
;
電控工程研究所
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Institute of Electrical and Control Engineering
A novel method using the charge pumping technique for extracting the effective channel length of MOSFET devices is presented, in which the effective area approach is used and the edges of the area are defined clearly. It is shown that the extracted effective channel length is independent of the measuring biases and the proposed new method is simple, accurate, and reliable, as compared to those using the I-V method. With the knowledge of the device dopant profiles, the extracted channel length with 0.01 mu m accuracy can be achieved. Moreover, the proposed method is applicable to either n- or p-channel, conventional or LDD, surface or buried channel MOSFET's.