Browsing by Author "LIN, CY"

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A COMPREHENSIVE STUDY OF SUPPRESSION OF BORON PENETRATION BY AMORPHOUS-SI GATE IN P+-GATE PMOS DEVICES
(1995-12-01)
LIN, CY
;
JUAN, KC
;
CHANG, CY
;
PAN, FM
;
CHOU, PF
This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p(+)-gate devices, The characteristics and reliability for different gate structures (poly-Si, alpha-Si, poly-Si/poly-Si, poly-Si/alpha-Si, alpha-Si/poly-Si, and alpha-Si/alpha-Si) in p(+) polygate PMOS devices are investigated in detail, The suppression of boron penetration by the nitrided gate oxide is also discussed, The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p(+) polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate, Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance, The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p(+)-gate PMOS device for future dual-gate CMOS process, In addition, by employing a long time annealing at 600 degrees C prior to p(+)-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate, Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect.
ANOMALOUS REVERSE SHORT-CHANNEL EFFECT IN P+ POLYSILICON GATED P-CHANNEL MOSFET
(1994-11-01)
CHANG, CY
;
LIN, CY
;
CHOU, JW
;
HSU, CCH
;
PAN, HT
The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p+ poly-gate PMOSFET's. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF2 doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator.
APPLICATION OF MULTICRITERIA DECISION-MAKING TO THE EVALUATION OF NEW ENERGY SYSTEM-DEVELOPMENT IN TAIWAN
(1992-10-01)
TZENG, GH
;
SHIAU, TA
;
LIN, CY
;
運輸與物流管理系註：原交通所+運管所
;
Department of Transportation and Logistics Management
The energy crisis in the 1970s and the recent rise in environmental protectionism have heightened interest in the introduction of new energy systems and the development of techniques to ensure the stability of the energy supply in Taiwan, where more than 90% of the supply is imported. In this study, a multicriteria evaluation method is employed to evaluate comprehensively the alternatives for new energy-system development. Energy technology, environmental impacts, sociology and economic factors were evaluated and development directions and strategy for future energy systems in Taiwan are proposed.
EFFECT OF OXYGEN IMPURITY ON MICROSTRUCTURE AND BORON PENETRATION IN A BF2+ IMPLANTED LPCVD STACKED AMORPHOUS-SILICON P(+) GATED PMOS CAPACITOR
(1995-07-01)
LIN, CY
;
PAN, FM
;
CHOU, PF
;
CHANG, CY
;
電控工程研究所
Secondary ion mass spectroscopy (SIMS) and transmission electron microscopy have been used to characterize microstructure and boron penetration in BF2+ implanted amorphous silicon p(+) gated metal oxide semiconductor (PMOS) capacitors, in which oxygen is inadvertently introduced in the gate area during the low pressure chemical vapor deposition (LPCVD) process. Oxygen impurity is found to be incorporated in the LPCVD deposited amorphous silicon film by SIMS. During the break between the two successive depositions for the stacked amorphous silicon (SAS) gate, an ultrathin oxide layer is formed at the interface between the two LPCVD amorphous silicon layers. The two thinner layers lead to smaller grains in the SAS structure. The interfacial oxide layer is a diffusion barrier for oxygen, which causes a higher oxygen concentration and, in turn, retards the crystallization in the SAS structure. Both the interfacial oxide layer and the gate oxide can dissolve a significant amount of fluorine after annealihg. Reduction of free fluorine near or in the gate oxide due to fluorine dissolution in the interfacial oxide layer plays a crucial role for suppressing the boron penetration in the SAS capacitor.
FEATURE MODIFICATION FRAMEWORK FOR FEATURE-BASED DESIGN SYSTEMS
(1995-02-01)
LI, RK
;
LIN, CY
;
WU, HH
;
交大名義發表
;
工業工程與管理學系
Design features created by a feature based design system could theoretically be directly sent to machining preparation system. This, however, has not been found and feature modification is still necessary. A feature modification framework is proposed in this paper for bridging the gap between the design features and machining features. Feature modification algorithms were also developed for the foundation of the framework. A prototype system is presented and illustrated by an explanation of how the feature modification concept could function in a real situation.
OPTIMAL TILE PARTITION FOR SPACE REGION OF INTEGRATED-CIRCUITS GEOMETRY
(1993-05-01)
HSIAO, PY
;
LIN, CY
;
SHEW, PW
;
資訊工程學系
;
Department of Computer Science
An optimal tile partition (OTP) is presented for partitioning the space region of a VLSI layout plane into rectangular space tiles. It modifies the corner stitching data structure to optimise the space tile partition. There is a serious restriction in the original corner stitching data structure, i.e. the solid rectangles cannot overlap each other, whereas our OTP allows overlapping. This paper also shows three theorems with rigorous proofs and experimental results to obtain the minimal number of the space tiles through the OTP. Moreover, a dynamic plane-sweep algorithm based on region query for the OTP has been developed. Using the OTP, the memory efficiency and the local query operations of the original corner stitching data structure have been enhanced.
SUPPRESSION OF BORON PENETRATION IN BF2-IMPLANTED P-TYPE GATE MOSFET BY TRAPPING OF FLUORINES IN AMORPHOUS GATE
(1995-08-01)
LIN, CY
;
CHANG, CY
;
HSU, CCH
;
電控工程研究所
;
奈米中心
This work reports the use of amorphous/polysilicon gate electrode in BF2-implanted poly-gated P-MOSFET's to suppress the boron penetration, SIMS analysis clearly illustrates that fluorine prefers to accumulate in the layer of amorphous silicon. The retardation of boron diffusion is therefore achieved by the trapping of fluorine in the amorphous layer of stacked amorphous/polysilicon (SAP) p-type gate due to a lower diffusion rate of fluorine in the amorphous silicon layer. Polysilicon depletion effect did not become more severe by introducing the amorphous silicon. In addition, gate oxide reliability is not degraded by using this gate structure. Results show that the structure is a promising gate electrode for future dual-poly gate CMOS technology development.