Browsing by Author "Lai, Bo-Cheng"

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A Novel Smart Assistance System for Blood Vessel Approaching: A Technical Report Based on Oximetry
(2020-04-01)
Lee, Chien-Ching
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Chuang, Chia-Chun
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Lai, Bo-Cheng
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Huang, Yi-Chia
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Chen, Jen-Yin
In clinical practice, the catheter has to be placed at an accurate position during anesthesia administration. However, effectively guiding the catheter to the accurate position in deeper tissues can be difficult for an inexperienced practitioner. We aimed to address the current issues associated with catheter placement using a novel smart assistance system for blood vessel catheter placement. We used a hollow introducer needle embedded with dual wavelength (690 and 850 nm) optical fibers to advance the tip into the subclavian vessels in anesthetized piglets. The results showed average optical density changes, and the difference between the absorption spectra and hemoglobin concentrations of different tissue components effectively identified different tissues (p < 0.05). The radial basis function neural network (RBFNN) technique was applied to distinguish tissue components (the F-measure value and accuracy were 93.02% and 94%, respectively). Finally, animal experiments were designed to validate the performance of the proposed system. Using this system based on oximetry, we easily navigated the needle tip to the target vessel. Based on the experimental results, the proposed system could effectively distinguish different tissue layers of the animals.
A Two-Directional BigData Sorting Architecture on FPGAs
(2020-01-01)
Lai, Bo-Cheng
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Chen, Chun-Yen
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Hsin, Yi-Da
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Lin, Bo-Yen
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電子工程學系及電子研究所
Sorting is pivotal data analytics and becomes challenging with intensive computation on drastically growing data volume. Sorting on FPGA has shown superior throughput, but the limited in-system memory causes vast data transferring to/from external storage when handling a large dataset. We propose a two-directional sorting (2DSort) architecture which sorts data sequences on both horizontal and vertical directions. 2DSort significantly reduces the costly data transmission by tracking the data on FPGA and writes back the data to external storage when the final sorting position is determined. 2DSort shows average 38.5 percent runtime enhancement in comparison to state-of-the-art bigdata sorting engine on FPGA.
Dual-wavelength fiber-optic technique to assist needle cricothyroidotomy
(1970-01-01)
Lee, Chien-Ching
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Chuang, Chia-Chun
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Lai, Bo-Cheng
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Lu, Chin-Li
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So, Edmund Cheung
The traditional needle cricothyroidotomy procedure is performed blindly without any medical equipment. Complications including posterior tracheal wall perforation, accidental vessel puncture, and missed tracheal puncture are reported. Therefore, we proposed a dual-wavelength fiber-optic technique based on the technique of near-infrared spectroscopy to assist operators performing needle cricothyroidotomy in a swine model. We embedded optical fibers in a 16-gauge intravenous needle catheter. Real-time data were displayed on an oscilloscope, and we used the program to analyze the data immediately. The change of optical density corresponding to 690-nm and 850-nm wavelengths and hemoglobin parameters (HbO(2)and Hb concentrations) was analyzed immediately using the program in the laptop. Unique and significant optical differences were presented in this experiment. We could easily identify every different tissue by the change of optical density corresponding to 690-nm and 850-nm wavelengths and hemoglobin parameters (HbO(2)and Hb concentrations). Statistical method (Kruskal-WallisHtest) was used to compare differences in tissues at each time-point, respectively. Thepvalues in every tissue in optical density change corresponding to 690 nm and 850 nm were all < 0.001. Furthermore, thepvalues in every tissue in Hb and HbO(2)were also all < 0.001. The results were statistically significant. This is the first and novel study to introduce a dual-wavelength embedded fibers into a standard cricothyroidotomy needle. This proposed system might be helpful to provide us real-time information of the advanced needle tip to decrease possible complications.
Efficient Write Scheme for Algorithm-based Multi-ported Memory
(2019-01-01)
Chen, Bo-Ya
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Chen, Bo-En
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Lai, Bo-Cheng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design.
Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks
(2019-05-01)
Lai, Bo-Cheng
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Pan, Jyun-Wei
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Lin, Chien-Yu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Although the existing single-instruction-multiple-data-like (SIMD) accelerators can handle the compressed format of sparse convolutional neural networks, the sparse and irregular distributions of nonzero elements cause low utilization of multipliers in a processing engine (PE) and imbalanced computation between PEs. This brief addresses the above issues by proposing a data screening and task mapping (DSTM) accelerator which integrates a series of techniques, including software refinement and hardware modules. An efficient indexing module is introduced to identify the effectual computation pairs and skip unnecessary computation in a fine-grained manner. The intra-PE load imbalance is alleviated with weight data rearrangement. An effective task sharing mechanism further balances the computation between PEs. When compared with the state-of-the-art SIMD-like accelerator, the proposed DSTM enhances the average PE utilization by 3.5x. The overall processing throughput is 59.7% higher than the previous design.
REMAP plus : An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory
(2020-03-01)
Lai, Bo-Cheng
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Chen, Bo-Ya
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Chen, Bo-En
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Hsin, Yi-Da
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電子工程學系及電子研究所
Supporting multiple write ports is one of the main challenges when designing algorithmic multiported memory (AMM). AMM supports concurrent accesses by cooperating multiple, low-complexity memory modules together with logical operations. When scaling the number of write ports, the nontable-based approaches quadratically increase the number of memory modules, whereas the table-based approaches tend to introduce complex lookup tables and access handling logics. In this article, we introduce REMAP+, an efficient banking architecture to support multiple writes. We optimize the pipeline of REMAP+ to achieve high access bandwidth and more efficient table access. We also exploit the structured architecture of REMAP+ and propose a systematic design flow to automate the scaling of write ports and optimization of banking. Comprehensive analysis is presented to reveal the insight into design features and concerns. Based on extensive experiments, we have shown that REMAP+ outperforms the existing write schemes (XOR, live value table (LVT), and REMAP) with higher bandwidth (49%, 50%, 18%), lower energy (28%, 49%, 54%), and smaller area (43%, 37%, 35%).
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors
(2014-08-01)
Pan, Gung-Yu
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Jou, Jing-Yang
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Lai, Bo-Cheng
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交大名義發表
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National Chiao Tung University
Dynamic power management has become an imperative design factor to attain the energy efficiency in modern systems. Among various power management schemes, learning-based policies that are adaptive to different environments and applications have demonstrated superior performance to other approaches. However, they suffer the scalability problem for multiprocessors due to the increasing number of cores in a system. In this article, we propose a scalable and effective online policy called MultiLevel Reinforcement Learning (MLRL). By exploiting the hierarchical paradigm, the time complexity of MLRL is O(n lg n) for n cores and the convergence rate is greatly raised by compressing redundant searching space. Some advanced techniques, such as the function approximation and the action selection scheme, are included to enhance the generality and stability of the proposed policy. By simulating on the SPLASH-2 benchmarks, MLRL runs 53% faster and outperforms the state-of-the-art work with 13.6% energy saving and 2.7% latency penalty on average. The generality and the scalability of MLRL are also validated through extensive simulations.
Selective bypassing and mapping for heterogeneous applications on GPGPUs
(2020-08-01)
Emara, Moustafa
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Lai, Bo-Cheng
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交大名義發表
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National Chiao Tung University
Modern GPGPU supports executing multiple tasks with different run time characteristics and resource utilization. Having an efficient execution and resource management policy has been shown to be a critical performance factor when handling the concurrent execution of tasks with different run time behavior. Previous policies either assign equal resources to disparate tasks or allocate resources based on static or standalone behavior profiling. Treating tasks equally cannot efficiently utilize the system resources, while the standalone profiling ignores the correlated impact when running tasks concurrently and could hint incorrect task behavior. This paper addresses the above drawbacks and proposes a heterogeneity aware Selective Bypassing and Mapping (SBM) to manage both computing and cache resources for multiple tasks in a fine-grain manner. The light-weight run time profiling of SBM properly characterizes the disparate behavior of the concurrently executed multiple tasks, and selectively applies suited cache management and workgroup mapping policies to each task. When compared with the previous coarse-grained policies, SBM can achieve an average of 138% and up to 895% performance enhancement. When compared with the state-of-art fine-grained policy, SBM can achieve an average of 58% and up to 378% performance enhancement. (C) 2020 Elsevier Inc. All rights reserved.
Supporting Compressed-Sparse Activations and Weights on SIMD-like Accelerator for Sparse Convolutional Neural Networks
(2018-01-01)
Lin, Chien-Yu
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Lai, Bo-Cheng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Sparsity is widely observed in convolutional neural networks by zeroing a large portion of both activations and weights without impairing the result. By keeping the data in a compressed-sparse format, the energy consumption could be considerably cut down due to less memory traffic. However, the wide SIMD-like MAC engine adopted in many CNN accelerators can not support the compressed input due to the data misalignment. In this work, a novel Dual Indexing Module (DIM) is proposed to efficiently handle the alignment issue where activations and weights are both kept in compressed-sparse format. The DIM is implemented in a representative SIMD-like CNN accelerator, and able to exploit both compressed-sparse activations and weights. The synthesis results with 40nm technology have shown that DIM can enhance up to 46% of energy consumption and 55.4% Energy-Delay-Product (EDP).
Towards high performance data analytic on heterogeneous many-core systems: A study on Bayesian Sequential Partitioning
(2018-12-01)
Lai, Bo-Cheng
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Wu, Tung-Yu
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Chiu, Tsou-Han
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Li, Kun-Chun
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Lee, Chia-Ying
Bayesian Sequential Partitioning (BSP) is a statistically effective density estimation method to comprehend the characteristics of a high dimensional data space. The intensive computation of the statistical model and the counting of enormous data have caused serious design challenges for BSP to handle the growing volume of the data. This paper proposes a high performance design of BSP by leveraging a heterogeneous CPU/GPGPU system that consists of a host CPU and a K80 GPGPU. A series of techniques, on both data structures and execution management policies, is implemented to extensively exploit the computation capability of the heterogeneous many-core system and alleviate system bottlenecks. When compared with a parallel design on a high-end CPU, the proposed techniques achieve 48x average runtime enhancement while the maximum speedup can reach 78.76x. (C) 2018 Elsevier Inc. All rights reserved.