Browsing by Author "Lai, Chih-Yen"

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A Read-Write Aware DRAM Scheduling for Power Reduction in Multi-Core Systems
(2014-01-01)
Lai, Chih-Yen
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Pan, Gung-Yu
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Kuo, Hsien-Kai
;
Jou, Jing-Yang
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電子工程學系及電子研究所
The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.
Power-Efficient Instancy Aware DRAM Scheduling
(2015-04-01)
Pan, Gung-Yu
;
Lai, Chih-Yen
;
Jou, Jing-Yang
;
Lai, Bo-Cheng Charles
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電子工程學系及電子研究所
Nowadays, computer systems are limited by the power and memory wall. As the Dynamic Random Access Memory (DRAM) has dominated the power consumption in modern devices, developing power-saving approaches on DRAM has become more and more important. Among several techniques on different abstract levels, scheduling-based power management policies can be applied to existing memory controllers to reduce power consumption without causing severe performance degradation. Existing power-aware schedulers cluster memory requests into sets, so that the large portion of the DRAM can be switched into the power saving mode; however, only the target addresses are taken into consideration when clustering, while we observe the types (read or write) of requests can play an important role. In this paper, we propose two scheduling-based power management techniques on the DRAM controller: the inter-rank read-write aware clustering approach greatly reduces the active standby power, and the intra-rank read-write aware reordering approach mitigates the performance degradation. The simulation results show that the proposed techniques effectively reduce 75% DRAM power on average. Compared with the existing policy, the power reduction is 10% more on average with comparable or less performance degradation for the proposed techniques.