Browsing by Author "Lai, Erh-Kun"

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A Novel Varying-Bias Read Scheme for MLC and Wide Temperature Range TMO ReRAM
(2016-11)
Lin, Yu-Hsuan
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Lee, Ming-Hsiu
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Wu, Jau-Yi
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Lin, Yu-Yu
;
Lee, Feng-Ming
Resistance of transition metal oxide (TMO) resistive random access memory (ReRAM) depends sharply on temperature, resulting in drastic memory window loss at high temperature. Thus, it is difficult to design the ReRAM that can serve a wide range of operating conditions. It is especially challenging to achieve multi-level-cell (MLC) ReRAM because of the large temperature dependency. This letter investigates both the temperature and read bias dependencies of WOx ReRAM, and found both can be well understood by a modified space-charge limited conduction model. Using this model, we have designed a novel read scheme that varies the read bias according to the device temperature and compensates for the temperature effect on cell resistance. Since TMO ReRAM devices depend on defect states, cell-to-cell and cycle-to-cycle variations are naturally large. An algorithm is designed to address the variability. A 1-Mb WOx ReRAM array is fabricated to both characterize the bias and temperature dependencies and verify the new read scheme. A large and constant memory window is preserved for MLC across a wide temperature range (-40 degrees C-125 degrees C), suitable for high-reliability applications.
Excellent High Temperature Retention of TiOXNV ReRAM by Interfacial Layer Engineering
(2018-01-01)
Lin, Yu-Hsuan
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Lee, Dai-Ying
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Wang, Chao-Hung
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Lee, Ming-Hsiu
;
Ho, Yung-Han
Since the resistance switching of the transition metal oxide (TMO) resistive random access memory (ReRAM) is based on thc interaction between the oxygen ions and vacancies, the unintentional oxygen/vacancy reaction should be avoided during data retention. This work demonstrates significant improvements on the retention performance by inserting a Si layer in the TiO Ny ReRAM to block the diffusion of oxygen ions through the Ti/TiO,N interface. The mechanism and factors that influenced thc IIRS and LRS retention arc also studied. The retention performance of HRS is correlated with its RESET level while the LRS retention depends on the programming current. The proposed Ti/Si/TiO,N, ReRAMs can switch for more than 103 cycles from array testing results.
Excellent Resistance Variability Control of WOx ReRAM by a Smart Writing Algorithm
(2016)
Lin, Yu-Hsuan
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Wu, Jau-Yi
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Lee, Ming-Hsiu
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Wang, Tien-Yen
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Lin, Yu-Yu
TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.
Study of the gate-sensing and channel-sensing transient analysis method for monitoring the charge vertical location of SONOS-type devices
(2007-09-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Lai, Erh-Kun
;
Huang, Tiao-Yuan
The gate-sensing and channel-sensing transient analysis method is studied in detail. This method introduces an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. Sensing in both modes provides two equations that are suitable to solve for two variables-the charge density (Q) and the average charge vertical location (x). In this paper, the principle of this method is discussed in detail. Several factors that affect the measurement accuracy are also analyzed. The power of this method is demonstrated by program/erase cycling and data retention tests. This method is indeed a powerful tool for detailed understanding of trapping dynamics.
Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs
(2010)
Lai, Erh-Kun
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Chien, Wei-Chih
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Chen, Yi-Chou
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Hong, Tian-Jue
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Lin, Yu-Yu
A complementary metal oxide semiconductor (CMOS)-compatible WO(x) based resistive memory has been developed. The WO(x) memory layer is made from rapid thermal oxidation of W plugs. The device performs excellent electrical properties. The switching speed is extremely fast (similar to 2 ns) and the programming voltage (< 1: 4 V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and 10(8)-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO(x) resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications. (C) 2010 The Japan Society of Applied Physics