Browsing by Author "Lai, Kuan-Ting"

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77-110 GHz 65-nm CMOS Power Amplifier Design
(2014-05-01)
Wu, Kun-Long
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Lai, Kuan-Ting
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Hu, Robert
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Jou, Christina F.
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Niu, Dow-Chih
This paper details the development of our millimeter-wave wideband power amplifier design. By treating the power combiner as an impedance transformer which allows different loading impedance to be taken into account, a compact wideband power-combining network can be constructed. With small transmission-line attenuation being sustained and maximum output power easily extracted from the transistors over the 77-110 GHz frequency range, a power amplifier can then be designed using 65-nm CMOS process to cover the whole W-band. In the on-wafer measurement, the gain is around 18 dB, the output reflection coefficients is below -10 dB, and the output-referred 1 dB compression point can reach 12 dBm at 1.2 V bias condition; when the bias is increased to 2.5 V, a 18 dBm output power is recorded. To our knowledge, this is the first CMOS power amplifier that covers the whole W-band.
77GHz Power Amplifier Design Using WIN 0.1 mu m GaAs pHEMT Process
(2014-01-01)
Lai, Kuan-Ting
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Wu, Kun-Long
;
Hu, Robert
;
Jou, Christina F.
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交大名義發表
This paper reports our 77GHz power-amplifier designs using WIN 0.1 mu m GaAs pHEMT process provided by the commercial WIN foundry. The first two stages of the power amplifier is made of common-source transistors for gain amplification, and then followed by two-and four-paralleled transistors where the 3dB two-way Wilkinson power splitters/combiners for large output power delivery are used. All the by-pass capacitors for drain and gate biases have been optimized to have small series impedance at W-band. The input DC-blocking capacitor is made coupled lines, which also functions as tuning circuit. With 2.5V and 350mA drain bias, the small-signal gain is 12dB, as measured on-wafer at room temperature; the output-referred 1dB compression point is 6dBm. With 3dBm input power, the saturated output power is around 8.6dBm. Good input- and output-port matching has also been observed. The chip size is 1000x2500 mu m(2) and it consumes 875mW.
DC-50GHz Wideband Phase-Compensated 90nm-CMOS Active Balun Design
(2015)
Wu, Kun-Long
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Lai, Kuan-Ting
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Hu, Robert
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Chang, Chi-Yang
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電機學院
This manuscript explores the output phase imbalance observed in the common-gate common-source transistors, and gives a mathematical formulation in determining the length of the compensation transmission line. To demonstrate the validity of this wideband phase-compensation technique, a DC-50GHz active balun is designed using commercial 90nm-CMOS process and then measured, where the phase imbalance is less than 5 degrees while the magnitude imbalance is within 1dB. All ports are well-matched and positive gain has been sustained up to 50GHz; the output-referred 1dB compression point is around 3dBm. With 3V and 32.5mA drain bias, the total power consumption is 97.5mW. To our knowledge, this is the widest active balun ever designed with such tight output phase requirement.