Browsing by Author "Lai, Ming-Fang"

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An implementation of performance-driven block and I/O placement for chip-package codesign
(2008)
Lai, Ming-Fang
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was developed by IBM is better suited for I/O increase than the typical peripheral wire-bond design. One of the most important characteristics of flip-chip designs is that the I/O buffers could be placed anywhere inside a chip, just like core cells. Motivated by [14] in proposing various I/O planning constraints, we develop a block and I/O buffer placement method in wirelength and signal skew optimization (especially for differential pair signals), and power integrity awareness for chip-package codesign. The results have shown that our approach takes care of power integrity and outperforms [12] in weighted performance metrics optimization.
Fast flip-chip pin-out designation respin by pin-block design and floorplanning for package-board codesign
(2007)
Lee, Ren-Jie
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Lai, Ming-Fang
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Chen, Hung-Ming
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface design has been a time-consuming process. This paper proposes a novel and efficient approach to designating pinout for flip-chip BGA package when designing chipsets. The proposed approach can not only automate the assignment of more than 200 I/O pins on package, but also precisely evaluate package size which accommodates all pins with almost no void pin positions, as good as the one from manual design. Furthermore, the practical experience and techniques in designing such interface has been accounted for, including signal integrity, power delivery and routability. This efficient pin-out designation and package size estimation by pin-block design and floorplanning provides much faster turn around time, thus enormous improvement in meeting design schedule. The results on two real cases show that our methodology is effective in achieving almost the same dimensions in package size, compared with manual design in weeks, while simultaneously considering critical issues in package-board codesign. To the best of our knowledge, this is the first attempt in solving flip-chip pin-out placement problem in package-board codesign.
Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies
(2011-11-01)
Lai, Ming-Fang
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Li, Shih-Wei
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Shih, Jian-Yu
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Chen, Kuan-Neng
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電子工程學系及電子研究所
Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment. Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application. (C) 2011 Elsevier B.V. All rights reserved.