Browsing by Author "Lai, Shin-Chi"

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11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids
(2015-06-01)
Lai, Shin-Chi
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Liu, Chih-Hao
;
Wang, Ling-Yi
;
Chen, Shin-Hao
;
Chen, Ke-Horng
This paper presents a novel algorithm and architecture design for 18-band quasi-class-2 ANSI S1.11 1/3 octave filterbank. The proposed design has several advantages such as lower group delay, lower computational complexity, and lower matching error. The technique we developed in this paper can be summarized as follows: 1) a simple low-pass filter (LPF) and discrete cosine transform (DCT) modulation are utilized to generate a uniform 9-band filterbank first, and then all elements of are replaced by all-pass filters to obtain a non-uniform filterbank; 2) a fast recursive structure and variable-length algorithm is further developed to efficiently accomplish DCT modulation. Thus, the spectrum of LPF can be easily spanned and flexibly extended to the location of the desired central frequency; 3) after employing the multi-rate algorithm, an 18-band non-uniform filterbank is generated from two 9-band sub filterbanks by following the proposed design steps and parameter determinations. Compared with the latest Liu et al.\'s quasi-class-2 ANSI S1.11 design, the proposed method-I (Proposed-I) totally has 72.8% reduction for multiplications per sample, 11.25-ms group delay, and 59 additions decreased per sample. Moreover, the maximum matching error of the proposed method-II (Proposed-II) is averagely equal to 1.79 dB much smaller than that of the latest Wei et al.\'s design. For the proposed variable-length DCT modulation, only 2 adders, 2 multipliers, 2 multiplexers, and 5 registers are required for hardware implementation after applying VLSI retiming scheme. Overall, the proposed filterbank design would be a new solution for future applications in the area of hearing aids.
120V/ns Output Slew Rate Enhancement Technique and High Voltage Clamping Circuit in High Integrated Gate Driver for Power GaN FETs
(2015)
Yang, Hsiang-An
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Chiu, Chao-Chang
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Lai, Shin-Chi
;
Chen, Jui-Lung
;
Chang, Chih-Wei
High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.
99.4% Peak Audio Signal Recovery Rate and Ultra-Low 0.32dB Matching Error with 10Hz High Resolution Filter Fitting Wearable Aided Speech Compensation System
(2015)
Lin, Yen-Ting
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Lai, Shin-Chi
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Chen, Shin-Hao
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Peng, Shen-Yu
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Chen, Ke-Horng
to get high sound quality, the proposed adaptive speech compensation (ASC) system fits psychoacoustic curves for individual needs. Moreover, characteristics of the speakers are considered by real-time speaker impedance estimation (RT-SIE) technique. Hence, original signal can be restored for every user with any speakers. ASC system has 99.4% peak original signal recovery rate by predicting and controlling output signal precisely. And the built-in 10Hz high resolution acoustic filter fitting scheme (AFFS) has less than 0.32dB matching error with an over 80dB hearing loss.
A 2.5W Tablet Speaker Delivering 3.2W Pseudo High Power by Psychoacoustic Model Based Adaptive Power Management System
(2014)
Chen, Shin-Hao
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Peng, Shen-Yu
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Chen, Ke-Horng
;
Lai, Shin-Chi
;
Kang, Sheng
for a 2.5W speaker in tablets, the proposed adaptive power management (APM) system can deliver a pseudo high power of 3.2W with a +/- 4V supply because it suppresses 0.7W power on tones that may damage a 2.5W speaker and escape the notice of human ears. With z-domain digital signal processing (z-DSP) and psychoacoustic model, high efficient power management and high sound quality can be achieved simultaneously. Conventional automatic gain control (AGC) only has the ability of 0.32W power suppression. Moreover, suppressing power by conventional clipping technique increases total-harmonic-distortion (THD). In contrast, the proposed real-time dynamic loading impedance (RT-DLI) monitoring brings forward a way to solve the problem on speaker damage while keeping low THD during high sound pressure level (SPL). THD in the APM system is slightly higher than that of original sound 1.1dB, comparing to the disadvantage of 8.6dB increasing caused by conventional clipping technique.
A 96%-Efficiency and 0.5%-Current-CrossRegulation Single-Inductor Multiple Floating-Output LED Driver with 24b Color Resolution
(2016)
Yang, Hsiang-An
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Yang, Wen-Hau
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Chen, Ke-Horng
;
Wey, Chin-Long
;
Lin, Ying-Hsi
A Low-Power Bio-Potential Acquisition System with Flexible PDMS Dry Electrodes for Portable Ubiquitous Healthcare Applications
(2013-03-01)
Chen, Chih-Yuan
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Chang, Chia-Lin
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Chang, Chih-Wei
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Lai, Shin-Chi
;
Chien, Tsung-Fu
This work describes a bio-potential acquisition system for portable ubiquitous healthcare applications using flexible polydimethylsiloxane dry electrodes (FPDEs) and a low-power recording circuit. This novel FPDE used Au as the skin contact layer, which was made using a CO2 laser and replica method technology. The FPDE was revised from a commercial bio-potential electrode with a conductive snap using dry electrodes rather than wet electrodes that proposed reliable and robust attachment for the purpose of measurement, and attaching velcro made it wearable on the forearm for bio-potential applications. Furthermore, this study proposes a recording device to store bio-potential signal data and provides portability and low-power consumption for the proposed acquisition system. To acquire differential bio-potentials, such as electrocardiogram (ECG) signals, the proposed recording device includes a low-power front-end acquisition chip fabricated using a complementary metal-oxide-semiconductor (CMOS) process, a commercial microcontroller (MSP430F149), and a secure digital (SD) card for portable healthcare applications. The proposed system can obtain ECG signals efficiently and are comfortable to the skin. The power consumption of the system is about 85 mW for continuous working over a 3 day period with two AA batteries. It can also be used as a compact Holter ECG system.
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform
(2016-03)
Lai, Shin-Chi
;
Juang, Wen-Ho
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Lee, Yueh-Shu
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Chen, Shin-Hao
;
Chen, Ke-Horng
This brief presents a hybrid structure to effectively compute the variable-length Fourier transform by employing the recursive and radix-2(2) fast algorithm. After applying a hardware-sharing scheme to both fast algorithms, the proposed method not only improves the drawback of higher hardware cost in implementation but also retains the regular and flexible nature of recursive discrete Fourier transform (RDFT). The proposed hardware accelerator only costs four real multipliers and ten real adders with a greater reduction (86.7% and 66.7%, respectively) than Kim et al.\'s design. In addition, the number of multiplications and additions for 256-point DFT computations can be reduced by 38.6% and 70%, respectively, compared to Lai et al.\'s recent approach. For accuracy analysis, the SNR value of the proposed design, at least, is 4 dB higher than the other RDFT designs. Considering a whole evaluation, a very-large-scale integration chip design was further fabricated using TSMC 0.18-mu m 1P6M CMOS process. The core size was only 660 x 660 mu m(2), and the measured power consumption was 8.8 mW @ 25 MHz. The result shows that the proposed chip included data memory is 1.38 times the computational efficiency per unit area of Lai et al.\'s work. Therefore, it will be the state-of-the-art RDFT processor in the application of various variable-transform-length digital signal processing issues.
Suppressing Output Overshoot Voltage Technique with 47.1mW/mu s Power-Recycling Rate and 93% Peak Efficiency DC-DC Converter for Multi-core Processors
(2015)
Chien, Meng-Wei
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Yang, Wen-Hau
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Chou, Ying-Wei
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Chen, Hsin-Chieh
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Chen, Wei-Chung
Conversion efficiency degrades in case of heavy-to-light loading change since state-of-art overshoot reduction techniques simply dissipate redundant energy at the output of buck DC-DC converter. Thus, the proposed dual-mode ripple-recovered compensator (D-RRC) and multi-phase suppressing output overshoot voltage (MP-SOOV) technique uses 33nH bondwire inductance to recycle energy and provides 47.1mW/mu s ultra-fast power-recycling rate to suppress overshoot voltage from 507mV to 95mV with 81.3% improvement when load changes from 1.7A to 0.3A. Experimental results show 93% high efficiency and high-speed operation with only tens of nano second on-time period.