Browsing by Author "Lai, Wei-Li"

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3D resistive RAM cell design for high-density storage class memory-a review
(2016-06)
Hudec, Boris
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Hsu, Chung-Wei
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Wang, I-Ting
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Lai, Wei-Li
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Chang, Che-Chia
In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO2-based filamentary 3D Vertical ReRAM as well as TaOx/TiO2 bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
Crossbar array of selector-less TaOx/TiO2 bilayer RRAM
(2015-11-01)
Chou, Chun-Tse
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Hudec, Boris
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Hsu, Chung-Wei
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Lai, Wei-Li
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Chang, Chih-Cheng
In this work, we have implemented self-rectifying TaOx/TiO2 REAM in a selector-less 6 x 6 crossbar array with various desiring features, including: (1) simple fabrication using only three masks, (2) high self-rectifying ratio up to 10(3) for sneak current suppression, (3) stable bipolar resistive-switching characteristics without the need for electro-forming and current compliance, (4) data retention time over 10(4) s, and (5) robust READ and WRITE disturb immunity. Finally, an achievable array size of 1 Mb was simulated using an All-LPU read scheme and a V/3 write scheme. (C) 2015 Elsevier Ltd. All rights reserved.
Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
(2014-04-25)
Hsu, Chung-Wei
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Wang, Yu-Fen
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Wan, Chia-Chen
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Wang, I-Ting
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Chou, Chun-Tse
Three-dimensional vertical resistive-switching random access memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive storage-class memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 10(3) with a sub-mu A operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 10(15) cycles at 100 degrees C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage memory by exploiting a unique tradeoff between retention time and endurance.
Interface engineered HfO2-based 3D vertical ReRAM
(2016-06-02)
Hudec, Boris
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Wang, I-Ting
;
Lai, Wei-Li
;
Chang, Che-Chia
;
Jancovic, Peter
We demonstrate a double-layer 3D vertical resistive random access memory (ReRAM) stack implementing a Pt/HfO2/TiN memory cell. The HfO2 switching layer is grown by atomic layer deposition on the sidewall of a SiO2/TiN/SiO2/TiN/SiO2 multilayer pillar. A steep vertical profile was achieved using CMOS-compatible TiN dry etching. We employ in situ TiN bottom interface engineering by ozone, which results in (a) significant forming voltage reduction which allows for forming-free operation in AC pulsed mode, and (b) non-linearity tuning of low resistance state by current compliance during Set operation. The vertical ReRAM shows excellent read and write disturb immunity between vertically stacked cells, retention over 10(4) s and excellent switching stability at 400 K. Endurance of 10(7) write cycles was achieved using 100 ns wide AC pulses while fast switching speed using pulses of only 10 ns width is also demonstrated. The active switching region was evaluated to be located closer to the bottom interface which allows for the observed high endurance.