Browsing by Author "Lai, Yan-Jiun"

Now showing 1 - 7 of 7

A 4.2 nW and 18 ppm/degrees C Temperature Coefficient Leakage-Based Square Root Compensation (LSRC) CMOS Voltage Reference
(2019-05-01)
Huang, Chao-Jen
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Lai, Yan-Jiun
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Yang, Yu-Jheng Ou
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Chen, Hung-Wei
;
Kuo, Chun-Chieh
State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1 similar to 1.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100 similar to 300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer sigma/mu of 0.204 and a TC of 18 ppm/degrees C with a power consumption of 4.2 nW.
A Fully Integrated Asymmetrical Shunt Switched-Capacitor DC-DC Converter With Fast Optimum Ratio Searching Scheme for Load Transient Enhancement
(2019-09-01)
Lin, Yen-Ting
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Lai, Yan-Jiun
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Chen, Hung-Wei
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Yang, Wen-Hau
;
Ma, Yu-Sheng
This paper presents a modified negator-based switched-capacitor (NSC) dc-dc converter to achieve fine-grained voltage conversion ratios. Based on a concept of reconfiguring several 2: 1 switched-capacitor (SC) converters in series and parallel at the last stage, the proposed asymmetrical shunt SC (ASSC) converter provides more controllable variables of forward gain and feedback gain to decide different power path interconnections and increase the available conversion ratios, with a little sacrifice of its slow switching limit output impedance. The switching loss of the bottom-plate parasitic capacitance in the ASSC converter is less than the switching loss of the NSC topology because the two moderate voltages instead of the power rail are fed to the last stage 2: 1 SC unit and reduce the voltage swing. The bottom-plate swapping prototype further reduces the parasitic loss at high conversion ratios. To handle a large number of conversion ratios in closed-loop regulation, the ASSC converter uses the fast optimum ratio searching (FORS) technique, which evaluates the transient voltage drop to quickly search for target ratios and reduce the transient recovery time. A three-stage ASSC converter achieving 187 conversion ratios is fully integrated in the test chip, which is fabricated in 0.25-mu m CMOS process with an active area of 7.14 mm(2). Furthermore, 2389 conversion ratios can be derived in theory for a four-stage ASSC converter. The proposed reconfigurable SC converter provides an output voltage range of 0.4 to 2.8 V under no load conditions, and greater than 80% power efficiency at an output voltage level of 0.9 to 1.5 V over a load range of 3 to 9.5 mA. Due to the FORS technique, the measured transient recovery time is reduced from 7 to 1.5 mu s in case of load current step of 7 mA.
A Three-Level Single-Inductor Triple-Output Converter with an Adjustable Flying-Capacitor Technique for Low Output Ripple and Fast Transient Response
(2017-01-01)
Chu, Li-Cheng
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Yang, Wen-Hau
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Zhang, Xiao-Qing
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Lai, Yan-Jiun
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Chen, Ke-Horng
A True-Random-Number-Based Pseudohysteresis Controller for Buck DC-DC Converter in High-Security Internet-of-Everything Devices
(2020-03-01)
Yang, Wen-Hau
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Chiu, Shao-Wei
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Kuo, Chun-Chieh
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Lin, Yen-Ting
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Lai, Yan-Jiun
For high-security Internet-of-Everything (IoE) devices, a true random number (TRN)-based pseudohysteresis controller (PHC) is proposed to avoid both power side-channel attack (PSCA) and power injection attack (PIA) and reduce electromagnetic interference (EMI) without degrading performance of transient response and regulation. In addition, the TRN-based PHC uses an enhanced security randomizer to correctly generate a random number (RN) independent of the input power at the PSCA and PIA and converts the RN into a hysteresis window that constitutes the true random modulation switching frequency. Therefore, the TRN-based PHC ensures proper spread spectrum and low EMI. In addition, fast transient response is maintained due to inherent hysteresis control. Experimental results show that peak EMI noise is reduced from 89.72 to 54.32dBV and meets the specification of EN 55032 Class B even under the PIA interference up to 1 V. Furthermore, in case of 0.2A-to-0.8A load step, the method achieves a recovery time of 7.3 s and an output voltage drop of 53 mV at a switching frequency of approximately 1 MHz, and the peak efficiency is 92.4.
An Enhanced-Security Buck DC-DC Converter with True-Random-Number-Based Pseudo Hysteresis Controller for Internet-of-Everything (IoE) Devices
(2018-01-01)
Yang, Wen-Hau
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Chu, Li-Cheng
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Yang, Shang-Hsien
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Lai, Yan-Jiun
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Chen, Shao-Qi
An Enhanced-Security Buck DC-DC Converter with True-Random-Number-Based Pseudo Hysteresis Controller for Internet-of-Everything (IoE) Devices
(2018-01-01)
Yang, Wen-Hau
;
Chu, Li-Cheng
;
Yang, Shang-Hsien
;
Lai, Yan-Jiun
;
Chen, Shao-Qi
Unsymmetrical Parallel Switched-Capacitor (UP-SC) Regulator with Fast Searching Optimum Ratio Technique
(2017-01-01)
Lin, Yen-Ting
;
Yang, Wen-Hau
;
Ma, Yu-Sheng
;
Lai, Yan-Jiun
;
Chen, Hung-Wei
Different from conventional multiphase switched-capacitor (SC) DC-DC converters, the proposed unsymmetrical parallel switched-capacitor (UP-SC) regulator provides more controllable input variables to increase available conversion ratios for improved load regulation. Even under higher conversion ratio numbers, the UP-SC regulator uses the fast searching optimum ratio (FSOR) technique to search the destined ratio rapidly and to reduce the transient recovery time. Experimental results show the test chip fabricated in 0.25 mu m CMOS process increases the ratio number to 187 and 2389 in 3-stage and 4-stage SC regulators, respectively. Transient recovery time reduces from 26 mu s to 1.5 mu s in case of 7mA load current step.