Browsing by Author "Lan, JF"

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CMOS current-mode neural associative memory design with on-chip learning
(1996-01-01)
Wu, CY
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Lan, JF
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Based on the Grossberg mathematical model called the outstar, a modular neural net with on-chip learning and memory is designed and analyzed. The outstar is the minimal anatomy that can interpret the classical conditioning or associative memory, It can also be served as a general-purpose pattern learning device. To realize the outstar, CMOS (complimentary metal-oxide semiconductor) current-mode analog dividers are developed to implement the special memory called the ratio-type memory. Furthermore, a CMOS current-mode analog multiplier is used to implement the correlation. The implemented CMOS outstar can on-chip store the relative ratio values of the trained weights for a long time. It can also be modularized to construct general neural nets, HSPICE (a circuit simulator of Meta Software, Inc.) simulation results of the CMOS outstar circuits as associative memory and pattern learner have successfully verified their functions, The measured results of the fabricated CMOS outstar circuits have also successfully confirmed the ratio memory and on-chip learning capability of the circuits, Furthermore, it has been shown that the storage time of the ratio memory can be as long as five minutes without refreshment, Also the outstar can enhance the contrast of the stored pattern within a long period, This makes the outstar circuits quite feasible in many applications.
Design, optimization, and performance analysis of new photodiode structures for CMOS active-pixel-sensor (APS) imager applications
(2004-02-01)
Wu, CY
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Shih, YC
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Lan, JF
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Hsieh, CC
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Huang, CC
The dark current in the active-pixel-sensor (APS) cell of a CMOS imager is known to be mainly generated in the regions of bird's beak after the local oxidation of silicon process as well as the surface damage caused by the implantation of high doping concentration. Furthermore, shallow and deep pn-junctions can improve the photo-sensitivity for light of short and long wavelengths, respectively. In this paper, two new photodiode structures using p-substrate and lightly-doped sensor implant SN- as pn-junction photodiode with the regions of bird's beak embraced by SN- and p-field implants, respectively, are proposed and analyzed to reduce dark current and enhance the overall spectral response. 5 mum x 5 pm APS cells fabricated in a 0.35-mum single-poly-triple-metal (1P3M) 3.3-V CMOS process are designed by using the proposed photodiode structures. As shown from the experimental results, the two proposed photodiode structures of 5 pin x 5 pm APS cells have lower dark currents of 30.6 mV/s and 35.2 mV/s at the reverse-biased voltage of 2 V and higher spectral response, as compared to the conventional structure and other photodiode structures. Thus, the two proposed new photodiode structures can be applied to CMOS imager systems with small pixel size, high resolution, and high quality.
The multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classification
(1997)
Lan, JF
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Wu, CY
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交大名義發表
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電子工程學系及電子研究所
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National Chiao Tung University
In this paper, a multi-chip expandable modified feedforward Hamming neural network for pattern classification is designed and implemented. In the proposed modified Hamming network, the outstar circuit is used to provide the on-chip learning capability. Moreover, the embedded ratio memory in the outstar circuit is used to store the learned pattern. The chips can be connected to form pattern, element, and pattern-and-element-mixed expansions. The experimental results have been correctly verified the operation of multi-chip expansion and classification function. The contrast enhancement characteristic of the stored pattern in the 3-chip element expansion has also been observed.