Browsing by Author "Lan-Da Van"

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Energy-Efficient FastICA Implementation for Biomedical Signal Separation
(2011-11-01)
Lan-Da Van
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Wu, Di-You
;
Chen, Chien-Shiun
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資訊工程學系
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Department of Computer Science
This paper presents an energy-efficient fast independent component analysis (FastICA) implementation with an early determination scheme for eight-channel electroencephalogram (EEG) signal separation. The main contributions are as follows: 1) energy-efficient FastICA using the proposed early determination scheme and the corresponding architecture; 2) cost-effective FastICA using the proposed preprocessing unit architecture with one coordinate rotation digital computer-based eigenvalue decomposition processor and the proposed one-unit architecture with the hardware reuse scheme; and 3) low-computation-time FastICA using the four parallel one-units architecture. The resulting power dissipation of the FastICA implementation for eight-channel EEG signal separation is 16.35 mW at 100 MHz at 1.0 V. Compared with the design without early determination, the proposed FastICA architecture implemented in united microelectronics corporation 90 nm 1P9M complementary metal-oxide-semiconductor process with a core area of 1.221 x 1.218 mm(2) can achieve average energy reduction by 47.63%. From the post-layout simulation results, the maximum computation time is 0.29 s.
FPGA-Oriented Real-Time EMD-Based Breath Signal Processing System on ARM11 MPCore Platform
(2018-01-01)
Lu, Tsung-Che
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Lin, Chien-Liang
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Chen, Pei-Yu
;
Lan-Da Van
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資訊工程學系
In this paper, a complete FPGA-oriented real-time empirical mode decomposition (EMD)-based breath signal processing system on ARM11 MPCore platform is developed. The system consists of three subsystems including biomedical signal acquisition, FPGA-oriented EMD accelerator and EMD processing result display. In this work, the previous published multiple stopping criteria and high IMFs Application Specific Integrated Circuit (ASIC)-oriented EMD accelerator is deployed to FPGA of ARM 11 MPCore platform such that the computation time of the overall system can he reduced. An external SRAM architecture in ARM 11 MPCore platform is adopted to process a large amount of data. The three subsystems are connected by a high speed internet such that real time data transportation is achieved. From the evaluation results, for 10K data size, the FPGA-oriented EMD accelerator can speed up by 29.21 times, 20.20 times, and 15.47 times compared with ARM11 processor running single core, dual cores, and four cores, respectively.
Type-3 2-D Multimode IIR Filter Architecture and the Corresponding Symmetry Filter's Error Analysis
(2017-01-01)
Chen, Pei-Yu
;
Lan-Da Van
;
Reddy, Hari C.
;
Khoo, I. H.
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資訊工程學系
In this paper, we propose a low-cost high-speed Type-3 two-dimensional (2-D) multimode symmetry IIR filter architecture including four different operation modes: diagonal symmetry mode (DSM), fourfold rotational symmetry mode (FRSM), quadrantal symmetry mode (QSM), and octagonal symmetry mode (OSM). For multimode purpose, the Type-3 transfer function is applied and the interconnections to achieve corresponding four symmetry filter architectures are proposed. The proposed 2-D IIR filter structure has lower number of adders and shorter critical path than the published Type-1 IIR filter structure without sacrificing multipliers. Furthermore, the theoretical error analysis of 2-D IIR filter architectures with diagonal symmetry and four-fold rotational symmetry is studied.