Browsing by Author "Laudato, Mario"

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Volatile Resistive Switching Memory Based on Ag Ion Drift/Diffusion Part I: Numerical Modeling
(2019-09-01)
Wang, Wei
;
Laudato, Mario
;
Ambrosi, Elia
;
Bricalli, Alessandro
;
Covi, Erika
Resistive-switching random access memory (RRAM) devices based on filamentary switching are attracting widespread interest for their unique properties, such as high ON-OFF ratio, ultrasteep slope, good endurance, and low-current operation. Recently, volatile RRAMs based on Ag drift and diffusion were also demonstrated for possible applications such as crosspoint array selectors and neuromorphic computing. However, the mechanism of the volatile switching, namely, the spontaneous dissolution of the Ag filament, is still not clear. A deep understanding of the metallic filament formation and spontaneous disruption would strongly help the engineering of the device for optimized performances. Here, we present a numerical physics-based drift/diffusion modeling framework to describe the threshold switching, I-V characteristics, and morphological evolution of the metallic filament. The model can support TCAD-type device simulations for scaling, reliability, and variability studies.
Volatile Resistive Switching Memory Based on Ag Ion Drift/Diffusion-Part II: Compact Modeling
(2019-09-01)
Wang, Wei
;
Laudato, Mario
;
Ambrosi, Elia
;
Bricalli, Alessandro
;
Covi, Erika
Resistive-switching random access memory (RRAM) based on Cu or Ag filament is a promising selector device for high-density crosspoint arrays. These devices display high ON-OFF ratio, volatile switching, high switching speed, and long endurance, supporting the adoption in large memory arrays. However, the mechanism of volatile switching is not clear yet, which prevents the development of compact models for circuit design and simulation. Based on an extensive study of the switching mechanism, we report an analytical model that captures all electrical characteristics of the device, including switching, recovery, and their dependence on the applied voltage. We use the analytical model to simulate the circuit-level behavior of the device as long/short term memory synapse.