Browsing by Author "Lee, C. -Y."

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Synthesis of porous micro-sized titania cages and their photocatalytic property
(2013-12-16)
Tsai, M. -C.
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Yang, M. -H.
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Chang, Y. -W.
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Tzeng, J. -K.
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Lee, C. -Y.
Micro-sized TiO2 cage consisted of anatase nanopartides on the edges of each cube, was synthesized using TTIP as the reagent and NaF submicrometer sized cubes as the template. When a salt of cube was adopted as the template, the reactants prefer to grow on the active sites, edges and corners of the cube, after removing the NaF template, the skeleton of the cube remain as the cage-shaped materials. The hierarchical structures with nano-sized anatase particles and micro scaled cage architecture markedly enlarge the surface area and enhance the light harvesting by light scattering of TiO2 frame, resulting in great photo-catalytic performance, which leads to the photo-degradation of methylene blue by 40% higher than that was achieved by crushed nanoparticles. (C) 2013 Elsevier B.V. All rights reserved.
Ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity
(2012-11-08)
Sung, W. -H.
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Lee, M. -C.
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Chung, C. -C.
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Lee, C. -Y.
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電子工程學系及電子研究所
An ultra-low voltage 22T implicit multiplexed differential (IMD) flip-flop (FF) is proposed. An implicit multiplexer is designed to simplify the differential FF complexity, while its control data path is able to enhance the FF noise immunity as well. So, the fully static IMD-FF with modified differential topology provides a sufficient noise margin under voltage scaling. On the other hand, the IMD-FF operation avoids considerable DC current dissipation to save active power and suppresses the idle leakage by stacked transistors. The post-layout simulation in 90 nm CMOS process with 400 mV supply voltage shows that the IMD-FF achieves 56% active power and 42.2% leakage power reduction. The tolerable noise energy is enhanced by 18.9% on average. Finally, this work provides 93% function yield rate under the effect of process-voltage-temperature variations and 40 pJ input noise energy.
Using Grid computing architecture in computing resource allocating of IC design
(1970-01-01)
Liu, Hongling
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Chen, Ruey-shun
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Lee, C. -Y.
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Cao, Wenliang
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Chen, Liping
At present, the utilization of workstation, storage, and server in an IC design house is not frequent, even the EDA license isn't, either. If these various resources on the intranet can be integrated and effectively operated, the working efficiency will be enhanced. Therefore, how to manage these critical resources on the network is a major task to enhance the competition of an IC design house.In this research, the Grid Engine structuring a model of resource distribution can integrate the resources on the intranet to build a set of system and rule about resource distribution. Taken the IC design house as an example, a user can use the technology of the Sun Grid Engine for load sharing, batch scheduling, as well as integration of resources of software/hardware on the intranet like a single workstation. Therefore, the working efficiency will be enhanced under limited resources because of complete utilization of system resources. The results of research provides a set of model and structure for management of system resources to integrate resources on the intranet in an IC design house. A resource distribution model can be established by the system and rule of resource distribution. According to the adequate management of computing resources as well as scheduling, the corresponding hardware and software can provide the computing service. Ultimately, the efficiency in software utilization increases twice and efficiency in hardware utilization increase. Besides, the purchase package expense can be reduced.
Wide duty cycle range synchronous mirror delay designs
(2010-03-04)
Sheng, D.
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Chung, C. -C.
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Lee, C. -Y.
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電機工程學系
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Department of Electrical and Computer Engineering
A wide duty cycle range and small static phase error synchronous mirror delay (SMD) for system-on-chip (SoC) applications is presented. The conventional SMD accepts only the pulsed clock signal and has large static phase error. The proposed SMD uses the edge-trigger mirror delay cell to enlarge the input duty cycle range and the blocking edge-trigger scheme to ensure functionality and performance. Moreover, phase error can be reduced by the proposed delay-matching structure and fine-tuning delay line with a high-resolution delay cell. Simulation results of SMD show that the input clock duty cycle range is from 20 to 80% and the worst static phase error under different process, voltage, and temperature conditions can achieve 18 ps at 400 MHz.