Browsing by Author "Lee, CE"

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A daily production model for wafer fabrication
(2004-01-01)
Pai, PF
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Lee, CE
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Su, TH
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工業工程與管理學系
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Department of Industrial Engineering and Management
The complex process and high variation in wafer fabrication make its production management very difficult. Problems such as planned target achievement and line balancing are not unusual in the industry. Such problems reveal the importance of developing a daily production policy for wafer fabrication. Planned target achievement and line balancing are the major concerns of this investigation in developing a daily production model. This investigation divides the process of wafer fabrication into two sections, i.e., the front and the rear, according to the last sputtering operation step. In the rear section, the objective is attaining the planned output target. In the front section, the major focus is to satisfy the demand of the rear section so that the production line is balanced. Release and dispatch policies are incorporated in this study to achieve both objectives. A real-world numerical example is used as simulation data. Results show that the proposed daily production model gives a better performance in the achievement of monthly planned output but suffers a little in the performance of line balancing.
A hybrid specification method for the design of a workcell controller in manufacturing systems
(2001)
Lai, HF
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Lee, CE
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工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper presents a hybrid specification method (HSM) for the description and design of a workcell controller in a manufacturing system. This hybrid method integrates the top-down IDEF0 and bottom-up statechart approaches. The high-level functional abstraction of a target system is first decomposed using IDEF0. Statecharts of the overall system are then combined using compositional constructs. programmable logic controller (PLCs) programs that represent the low-level abstraction are finally transformed from the statecharts. To demonstrate the viability of this method, an example of a workcell controller is designed using this method. The proposed method provides an alternative to the traditional top-down decomposition technique with reusable and extendable properties.
A total standard WIP estimation method for wafer fabrication
(2001-05-16)
Lin, YH
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Lee, CE
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工業工程與管理學系
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Department of Industrial Engineering and Management
The standard work-in-process (WIP) level in a wafer fabrication factory is an important parameter which can be properly used to trigger the decision of when to release specific wafer lots. There are many WIP-based release control policies which have been proven to be effective for wafer fabrication manufacturing, few methods have been proposed to find the suitable WIP-level as a parameter for these release policies. This paper proposes a queueing network-based algorithm to determine the total standard WIP level so that the Fixed-WIP release algorithm to determine the total standard WIP level so that the Fixed-WIP release control policy can apply. A numerical example is provided to elaborate the algorithm. A simulation model of a real-world wafer fabrication factory in Taiwan is built and analyzed. Results of simulation experiment indicate that under the Fixed-WIP control policy, the total standard WIP level estimated from this study achieves a target throughput rate while keeping the corresponding cycle time relatively low. Results also demonstrate that the queueing network-based algorithm is a very useful method to determine the standard WIP level efficiently. (C) 2001 Elsevier Science B.V. All rights reserved.
A two-machine flowshop scheduling heuristic with bicriteria objective
(1998-06-01)
Lee, CE
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Chou, FD
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工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper presents a O(N-2) heuristic algorithm to solve the two-machine flowshop scheduling with bicriteria objective to minimize the sum of makespan and total flow time. An integer programming model with N-2+2N variables and 3N constraints is also formulated to validate the performance of the heuristic scheduling algorithm proposed here. Experimental results demonstrate that the proposed algorithm can efficiently solve this problem with a high solution quality. Although the integer programming model provides the optimal solution, variables and constraints markedly increase when the number of jobs increases. Therefore, the optimal solution is not always attainable within the allowable time. The heuristic algorithm is much more practical in real world applications than the integer programming model.
A WIP estimation model for wafer fabrication
(2002-09-01)
Lin, YH
;
Lee, CE
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
The standard WIP (work-in-process) level in wafer fabrication is an important parameter which can be used to diminish system disturbances. This parameter can also be used to trigger the decisions of when to release particular wafer lots and how to dispatch them. This paper not only explores the significance of standard WIP in wafer fabrication, but also presents a method, based on the reorder point (ROP) model, to estimate the standard WIP level in front of each workstation. A numerical example illustrates the method's effectiveness. Also, a simulation model of a real-world wafer fabrication factory in Taiwan is constructed and the wafer input control rule, Fixed-WIP, is applied. Results of a single factor experimental design indicate that the standard WIP level estimated in this study achieves a short mean cycle time and an acceptably high mean throughput rate. The phenomenon, occurring throughout this study, in which a lower WIP level does not guarantee a shorter average cycle time in wafer fabrication, is also explored. Results presented herein demonstrate that the ROP-based WIP estimation method is a highly efficient method in deter-mining a safe and reliable standard WIP level during wafer fabrication.
Downgrading and release rules for control and dummy wafers
(2004-06-01)
Chen, HC
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Lee, CE
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工業工程與管理學系
;
Department of Industrial Engineering and Management
A variety of control and dummy wafers (CD wafers) are utilized in wafer fabrication to enhance product quality and process stability. Wafer fabs downgrade and recycle used CD wafers for cost-down purposes. Downgrading and release rules therefore become crucial issues in CD-wafer management activities but only few studies covered this topic. This study presents a CD-wafer management system, the push system, focusing on downgrading and release rules. The push system attempts to reduce machine delay time, increase recycled usages of CD-wafer lots, and attain a reasonable CD-wafer work-in-process (WIP) level without lowering the throughput rate of product wafers. This study also employs a simulation model of a simplified fab to analyze the performance of the proposed push system. Simulation results demonstrate that the push system leads to efficient utilization of CD wafers. Significance: This work proposes a systematic system, the push system, for downgrading and releases of control and dummy wafers in wafer fabrication. The issue discussed in this study is crucial and practical for wafer fabrication but is seldom cited in research papers.
Outsourcing capacity planning for an an IC design house
(2004-08-01)
Lee, CE
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Hsu, SC
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工業工程與管理學系
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Department of Industrial Engineering and Management
The management of outsourcing capacity is one of the key issues for IC design houses. There are two fundamental problems in outsourcing capacity management; they are the estimation of net capacity and the allocation of capacity. The purpose of this paper is to propose a framework of outsourcing capacity planning (OCP) for an IC design house to solve these two problems. The framework of OCP contains three parts: Net IC Product Demand Planning, Net Capacity Demand Planning, and Booking Capacity Planning. Linear Programming (LP) is employed to generate a net IC demand plan. A transformation process that transforms net IC product demand into net capacity demand is applied to obtain the net capacity demand plan. Finally, we use Analytic Hierarchy Process (AHP) to combine the factors, which an IC design house considers for outsourcing, into a Utility Index (U.I.). We then employ U.I. to develop a heuristic method to deal with the booking capacity planning problem. The result of OCP yields a better performance than that of the practice approach. In addition, OCP provides a decision procedure to assist IC design houses in monitoring the performance of each subcontractor.
Two-machine flowshop scheduling with bicriteria problem
(1999-07-01)
Chou, FD
;
Lee, CE
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper attempts to solve a two-machine flowshop bicriteria scheduling problem with release dates for the jobs, in which the objective function is to minimize a weighed sum of total flow time and makespan. To tackle this scheduling problem, an integer programming model with N-2 + 3N variables and 5N is the number of jobs, is formulated. Because of the lengthy computing time and high computing complexity of the integer programming model, a heuristic scheduling algorithm is presented. Experimental results show that the proposed heuristic algorithm can solve this problem rapidly and accurately. The average solution quality of the heuristic algorithm is above 99% and is much better than that of the SPT rule as a benchmark. A 15-job case requires only 0.018 s, on average to obtain an ultimate or even optimal solution. The heuristic scheduling algorithm is a more practical approach to real world applications than the integer programming model. (C) 1999 Published by Elsevier Science Ltd. All rights reserved.