Browsing by Author "Lee, CF"

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3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-kappa dielectric on 1P6M-0.18 mu m-CMOS
(2004)
Yu, DS
;
Chin, A
;
Laio, CC
;
Lee, CF
;
Cheng, CF
For the first time, we demonstrate 3D integration of self-aligned IrO2(Hf)/LaAlO3/GOI CMOSFETs above 0.18 pm Si CMOSFETs. At EOT=1.4nm, the novel IrO2(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO3/Si devices have high electron and hole mobilities of 203 and 67 cm(2)/Vs. On the 3D structure the LaAlO3/GOI shows even higher 389 and 234 cm(2)/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.
A new application of fuzzy set theory to the Black-Scholes option pricing model
(2005-08-01)
Lee, CF
;
Tzeng, GH
;
Wang, SY
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科技管理研究所
;
資訊管理與財務金融系註：原資管所+財金所
The Black-Scholes Option pricing model (OPM) developed in 1973 has always been taken as the cornerstone of option pricing model. The generic applications of such a model are always restricted by its nature of not being suitable for fuzzy environment since the decision-making problems occurring in the area of option pricing are always with a feature of uncertainty. When an investor faces an option-pricing problem, the outcomes of the primary variables depend on the investor's estimation. It means that a person's deduction and thinking process uses a non-binary logic with fuzziness. Unfortunately, the traditional probabilistic B-S model does not consider fuzziness to deal with the aforementioned problems. The purpose of this study is to adopt the fuzzy decision theory and Bayes' rule as a base for measuring fuzziness in the practice of option analysis. This study also employs 'Fuzzy Decision Space' consisting of four dimensions, i.e. fuzzy state; fuzzy sample information, fuzzy action and evaluation function to describe the decision of investors, which is used to derive a fuzzy B-S OPM under fuzzy environment. Finally, this study finds that the over-estimation exists in the value of risk interest rate, the expected value of variation stock price, and in the value of the call price of in the money and at the money, but under-estimation exists in the value of the call price of out of the money without a consideration of the fuzziness. (C) 2005 Elsevier Ltd. All fights reserved.
A tunable and program-erasable capacitor on Si with excellent tuning memory
(2004)
Lai, CH
;
Lee, CF
;
Chin, A
;
Zhu, C
;
Li, MF
A novel tunable and program-erasable high-kappa: AIN MIS capacitor is demonstrated for the first time with excellent tuning memory, which is useful to tune the impedance mismatching and resonance frequency without always connected voltage bias circuit. Large C-max /C-min tunability of 12 is obtained due to the high-kappa AIN dielectric with high 5 muF/mum(2) capacitance density. Good tuning memory is evidenced from the small V-th variation after program or erase at +4 V or -4 V for 10,000 s and the potential of years long extrapolated memory time.
An empirical analysis of the relationship between the hedge ratio and hedging horizon: A simultaneous estimation of the short- and long-run hedge ratios
(2004-04-01)
Chen, SS
;
Lee, CF
;
Shrestha, K
;
資訊管理與財務金融系註：原資管所+財金所
;
Department of Information Management and Finance
This article analyzes the effects of the length of hedging horizon on the optimal hedge ratio and hedging effectiveness using 9 different hedging horizons and 25 different commodities. We discuss the concept of short- and long-run hedge ratios and propose a technique to simultaneously estimate them. The empirical results indicate that the short-run hedge ratios are significantly less than 1 and increase with the length of hedging horizon. We also find that hedging effectiveness increases with the length of hedging horizon. However, the long-run hedge ratio is found to be close to the naive hedge ratio of unity. This implies that, if the hedging horizon is long, then the naive hedge ratio is close to the optimum hedge ratio. (C) 2004 Wiley Periodicals, Inc.
Growth temperature reduction for isoelectronic As-doped GaN
(2003-03-01)
Lee, WH
;
Huang, HY
;
Chen, WC
;
Lee, CF
;
Chen, WK
As-doped GaN films were grown at different temperatures by atmospheric metalorganic chemical vapor deposition. A higher electron Hall mobility, narrower line width in photoluminescence, and longer spatial correlation length of the filmes were obtainable at low growth temperatures compared to undoped GaN grown at the same temperatures as a result of isoelectronic As-doping.
Low noise RF MOSFETs on flexible plastic substrates
(2005-07-01)
Kao, HL
;
Chin, A
;
Hung, BF
;
Lee, CF
;
Lai, JM
We report a low minimum noise figure (NFmin) of 1.1 dB and high associated gain (12 dB at 10 GHz) for 16 gate-finger 0.18-mu m RF MOSFETs, after thinning down the Si substrate to 30 mu m and mounting it on plastic. The device performance was improved by flexing the substrate to create stress, which produced a 25% enhancement of the saturation drain current and lowered NFmin to 0.92 dB at 10 GHz. These excellent results for mechanically strained RF MOSFETs on plastic compare well with 0.13-mu m node (L-g = 80 nm) devices.
Modeling finger number dependence on RF noise to 10 GHz in 0.13 mu m node MOSFETs with 80nm gate length
(2004)
King, MC
;
Lai, ZM
;
Huang, CH
;
Lee, CF
;
Ma, MW
We have modeled the as-measured and de-embedded NFmin on multi-fingers 0.13 mum node MOSFETs. In contrast to the as-measured large NFmin value and strong dependence on parallel gate fingers, the de-embedded NFmin. has much smaller noise of only 1.1-1.2 dB for 6, 18 and 36 fingers and weak dependence. From the well calibrated equivalent circuit model with as-measured NFmin, the dominant noise source is from the probing pad generated thermal noise. From our derived equation with excellent agreement with de-embedded NFmin to 10 GHz, the weak dependence of intrinsic NFmin on gate finger is due to the combined effect of R(g)g(m) and drain hot carrier noise but both have weak dependence on finger numbers.
Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout
(2005)
Kao, HL
;
Chin, A
;
Lai, JM
;
Lee, CF
;
Chiang, KC
A novel microstrip line layout is developed to direct measure the min. noise figure (NFmin) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NFmin of 1.05 dB at 10 GHz is directly measured in 16 gate fingers 0.18 mu m MOSFETs without any de-embedding. Based on the accurate NFmin measurement, we have developed the self-consistent DC, S-parameters and NFmin model to predict device characteristics after the continuous stress with good accuracy.
Plausible origin of electromigration lifetime extrapolation difference between wafer level isothermal test and package level constant current test
(2004)
Wang, CS
;
Chen, MJ
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Chang, WC
;
Ke, WS
;
Lee, CF
Electromigration lifetime extrapolated from the wafer level isothermal test on a metal line does not coincide with that from the package level constant current test. The discontinuity of mass flux density in wafer level isothermal test as origin of such difference is identified based on a temperature profile along the metal line. Once this issue is clarified in advance, improved correlation between both tests can be achieved and as a result, wafer level isothermal test is expected to replace the conventional time-consuming package level constant current test.
Reducing AC power consumption by three-dimensional integration of Ge-on-insulator CMOS on 1-poly-6-metal 0.18 mu m Si MOSFETs
(2005)
Yu, DS
;
Liao, CC
;
Chen, CC
;
Lee, CF
;
Cheng, CF
We have used three-dimensional (3D) integration to reduce the ac power consumption in interconnects, which is the most severe issue beyond the dc power arising from the gate dielectric leakage current. From a direct calculation of the ac power consumption using an electromagnetic method, we show that both the ac power consumption and maximum operation frequency can be improved by integrating an additional integrated circuit layer. The 3D integration was realized by Ge-on-insulator (GOI) complementary metal oxide semiconductor field effect transistors (CMOSFETs) on 1-poly-6-metal (1P6M) 0.18 mu m Si devices, where little performance degradation was measured in the lower layer 0.18 mu m Si MOSFETs, due to the inherent low thermal budget (500 degrees C rapid thermal anneal) of the GOI processing. The drive current of the 3D GOI n- and p-MOSFETs was more than double that of the control Si devices, providing another advantage of the approach. (c) 2005 The Electrochemical Society. All rights reserved.
Series quartz crystal sensor for remote bacteria population monitoring in raw milk via the Internet
(2006-02-15)
Chang, KS
;
Jang, HD
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Lee, CF
;
Lee, YG
;
Yuan, CJ
A remote monitoring system based on a piezoelectric quartz crystal (SPQC) sensor was developed for the determination of the bacteria population in raw milk. The system employs the Windows XP server operating system, and its programs for data acquisition, display and transmission were developed using the LabVIEW 7.1 programming language. The circuit design consists of a circuit with a piezoelectric quartz crystal (SPQC) and a pair of electrodes. This system can provide dynamic data monitoring on a web-page via the Internet. Immersion of the electrodes in a cell culture with bacteria inoculums resulted in a change of frequency caused by the impedance change due to microbial metabolism and the adherence of bacteria on the surface of the electrodes. The calibration curve of detection times against density of bacteria showed a linear correlation coefficient (R-2 = 0.9165) over the range of 70-10(6) CFU ml(-1). The sensor could acquire sufficient data rapidly (within 4 h) and thus enabled real-time monitoring of bacteria growth via the Internet. This system has potential application in the detection of bacteria concentration of milk at dairy farms. (c) 2005 Elsevier B.V. All rights reserved.
Strain-induced very low noise RF MOSFETs on flexible plastic substrate
(2005)
Kao, HL
;
Chin, A
;
Hung, BF
;
Lai, JM
;
Lee, CF
Using microstrip line design to screen substrate resistance generated RF noise, very low 1.1 dB min. noise figure (NFmin) and high 12 dB associate gain are measured at 10 GHz of 0.18 mu m MOSFET on plastic without de-embedding. The die on plastic was thinned to 30 mu m that allows applying uniaxial strain to further lower the 10 GHz NFmin to only 0.92 dB and comparable well with the 0.13 mu m and 90nm nodes MOSFETs.
Systematic analysis of the offset-PLL output spur spectrum
(2005-09-01)
Lee, CF
;
Peng, ST
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電信工程研究所
;
Institute of Communications Engineering
This paper presents a mechanism that explains exactly the cause of spurs at the output of offset-PLL (OPLL) transmitters. By a rigorous analysis of the relationship between the signals and disturbances in OPLL, accurate formulas are obtained which elucidate systematically the intermodulation nature of the output sour spectrum. From the, analysis, it is shown that in practical situations the OPLL spurs are due to the disturbances from the voltage-controlled oscillator leakage, the local oscillator leakage, and the image signal, rather than other spurious products of the offset mixer in the loop as previously explained. The formulas give insight into OPLL circuit design and frequencies accommodation and clearly depict the output spur distribution in the more realistic situation when the input is modulated. Finally, the formulas are verified by some elaborate experiments with extensive numerical results.
Three-dimensional metal gate-high-kappa-GOI CMOSFETs on 1-poly-6-metal 0.18-mu m Si devices
(2005-02-01)
Yu, DS
;
Chin, A
;
Liao, CC
;
Lee, CF
;
Cheng, CF
We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-Insulator (GOI) CMOSFETs above 0.18-mum Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO3-GOI p-MOSFETs and IrO2-Hf-LaAlO3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm(2)/Vs respectively, without depredating the underneath 0.18-mum Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.
Time domain equalization for DMT transceivers: A new result
(2005)
Wu, WR
;
Lee, CF
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電信工程研究所
;
Institute of Communications Engineering
The time-domain equalizer (TEQ) is a commonly used device to shorten the channel impulse response a discrete multitone (DMT) receiver. With a capacity maximization criterion, many methods have been proposed to solve the TEQ problem. However, due to a mis-calculation of noise power, the optimal solutions claimed are actually not optimal. Since the noise component in a DMT symbol does not have cyclic prefix, the discrete-Fourier transform (DFT) of the TEQ-filtered noise does not equal to the DFT of the TEQ multiplied by that of noise. In this paper, we analyze the TEQ-filtered noise in detail and derive the correct noise power calculation formulae. Based on the result, we propose a new TEQ design method outperforming existing ones.
Very low noise RIF nMOSFETs on plastic by substrate thinning and wafer transfer
(2005-11-01)
Kao, HL
;
Hung, BF
;
Chin, A
;
Lai, JM
;
Lee, CF
A very low minimum noise figure (NFmin) of 1.2 dB and a high associated gain of 12.8 dB at 10 GHz were measured for six-finger, 0.18-mu m radio frequency (RF) metal-oxide semiconductor field-effect transistors mounted on insulating plastic following substrate-thinning (similar to 30 mu m) and wafer transfer. Before this process, the devices had a slightly better RF performance of 1.1-dB NFmin anda 13.7-dB associated gain. The small RF performance degradation of the active transistors transferred to plastic shows the potential of integrating electronics onto plastic.