Browsing by Author "Lee, Chen-Ming"

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A High-Performance 30-nm Gate-All-Around Poly-Si Nanowire Thin-Film Transistor With NH(3) Plasma Treatment
(2010-07-01)
Lee, Chen-Ming
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel 30-nm gate-all-around (GAA) polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistor (TFT) is reported for the first time. Owing to the NW and GAA structure, the channel electric potential is well controlled by the gate electrode. After NH(3) plasma treatment for defects passivation, the values of 0.97 V, 224 mV/dec., and 0.895 V/V of threshold voltage, subthreshold swing, and drain-induced barrier lowering are achieved, respectively. A high driving current of 459 mu A/mu m and an ON-state/OFF-state current ratio of 5 x 10(7) are also obtained. These excellent characteristics indicate that the ultrasmall GAA NW poly-Si TFT would have the potential to be applied in the 3-D integrated-circuit or system-on-panel field.
A High-Performance 30-nm Gate-All-Around Poly-Si Nanowire Thin-Film Transistor With NH3 Plasma Treatment
(2010-07-01)
Lee, Chen-Ming
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel 30-nm gate-all-around (GAA) polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistor (TFT) is reported for the first time. Owing to the NW and GAA structure, the channel electric potential is well controlled by the gate electrode. After NH3 plasma treatment for defects passivation, the values of 0.97 V, 224 mV/dec., and 0.895 V/V of threshold voltage, subthreshold swing, and drain-induced barrier lowering are achieved, respectively. A high driving current of 459 mu A/mu m and an ON-state/OFF-state current ratio of 5 x 10(7) are also obtained. These excellent characteristics indicate that the ultrasmall GAA NW poly-Si TFT would have the potential to be applied in the 3-D integrated-circuit or system-on-panel field.
High-Performance Poly-Si Nanowire Thin-Film Transistors Using the HfO(2) Gate Dielectric
(2011-03-01)
Lee, Chen-Ming
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) using hafnium dioxide (HfO(2)) as gate dielectric is successfully fabricated for the first time. The excellent short-channel characteristics are attributed to the high-kappa gate dielectric, ultrathin poly-SiNW channel thickness, and omega-shaped gate structure. The record high driving capability of 549 mu A/mu m results from the ultrashort gate length (L(G)), thin equivalent oxide thickness, and Ni silicide metal source/drain. This letter reveals the opportunity of high-performance poly-Si TFT circuits for system-on-panel and 3-D integrated circuit (3-D IC) applications.
High-Performance Poly-Si Nanowire Thin-Film Transistors Using the HfO2 Gate Dielectric
(2011-03-01)
Lee, Chen-Ming
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) using hafnium dioxide (HfO2) as gate dielectric is successfully fabricated for the first time. The excellent short-channel characteristics are attributed to the high-kappa gate dielectric, ultrathin poly-SiNW channel thickness, and omega-shaped gate structure. The record high driving capability of 549 mu A/mu m results from the ultrashort gate length (L-G), thin equivalent oxide thickness, and Ni silicide metal source/drain. This letter reveals the opportunity of high-performance poly-Si TFT circuits for system-on-panel and 3-D integrated circuit (3-D IC) applications.
Random Telegraph Signal Noise Arising from Grain Boundary Traps in Nano-scale Poly-Si Nanowire Thin-Film Transistors
(2013)
Lee, Chen-Ming
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Nano-scale poly-Si thin-film transistor (TFT) is a promising device for the three-dimensional integrated circuits (3D IC) and 3D stacked flash memories. Random telegraph signal noise (RTN) arising from grain boundary traps is identified and a grain-boundary-induced-fluctuation (GBIF) model is proposed for the first time. Amonia plasma treatment can suppress this RTN source effectively.
Thermal Stability of Nickel Silicide and Shallow Junction Electrical Characteristics with Carbon Ion Implantation
(2010)
Tsui, Bing-Yue
;
Lee, Chen-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, we investigated the impact of carbon ion implantation on the thermal stability of nickel silicide film and nickel-silicide-contact n(+)/p shallow junctions. A higher carbon ion implantation dose can prevent the nickel silicide film from agglomeration and phase transformation. However, good thermal stability does not necessarily lead to excellent junction current-voltage characteristics owing to the diffusion of nickel atoms. When the carbon ion implantation dose increases to 5 x 10(15) cm(-2), many crystal defects are created. Then, numerous nickel atoms diffuse along these defects into the junction depletion region during the silicide formation process, resulting in poor junction characteristics. The trade-off between thermal stability and junction electrical characteristics is discussed in this paper. Finally, two methods are suggested to solve the serious leakage current problem. (C) 2010 The Japan Society of Applied Physics