Browsing by Author "Lee, Chen-Yi"

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A (50,2,4) Nonbinary LDPC Convolutional Code Decoder Chip over GF(256) in 90nm CMOS
(2012)
Lin, Chia-Lung
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電機學院
A memory-based (m(s) = 50, d(v) = 2, d(c) = 4) nonbinary LDPC convolutional code (NB-LDPC-CC) decoder over GF(256) with layered scheduling is presented. The proposed architecture-aware construction features fewer memory banks, low degree, low period, and better performance. To the best of our knowledge, this is the first architecture discussion and implementation for NB-LDPC-CC decoders. We optimized the architecture of message first-in-first-out (M-FIFO), check node unit, and variable node unit in terms of area and throughput. Jointly designing code and architecture, overall normalized area efficiency can be enhanced by more then six times with respect to decoders of nonbinary LDPC block codes (NB-LDPC BCs). After fabricated in 90nm CMOS, our prototype NB-LDPC-CC decoder chip can achieve maximum throughput of 22.8Mbps with frequency of 285MHz. The measured average power is 211mW at a typical operating voltage of 1.0V.
A 0.0354mm(2) 82 mu W 125KS/s 3-Axis Readout Circuit for Capacitive MEMS Accelerometer
(2013)
Lai, Kelvin Yi-Tse
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He, Zih-Cheng
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Yang, Yu-Tao
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Chang, Hsie-Chia
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Lee, Chen-Yi
In this paper, we propose a power/area-efficient capacitive readout circuit for the Micro-Electro-Mechanical Systems (MEMS) sensor of 3-axis accelerometer. The proposed architecture is different from other traditional structures by exploiting true capacitive-to-digital converter (CDC) without Analog-to-Digital Converter (ADC). The proposed CDC can differentiate the bidirectional 125KS/s 80-level accelerations between +/- 8g and support the 4-level adjustable resolutions of 0.1g/0.2g/0.4g/0.8g for each axis. The proposed readout circuit with 0.0354mm(2) area is fabricated in UMC 0.18um CMOS-MEMS process. Experimental results show power consumption is 50uW with 1.8V supply voltage for 1-axis (FOM=3.84pJ), 82uW for 3-axis (FOM=2.1pJ) under 125KHz of sampling frequency and 0.1g acceleration sensitivity for 0.2fF MEMS capacitance change.
A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
(2007)
Wong, Cheng-Chi
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Tang, Cheng-Hao
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Lai, Ming-Wei
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Zheng, Yan-Xiu
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Lin, Chien-Ching
This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 mu m CMOS process, the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s data rate.
A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications
(2009-11-01)
Chen, Tsan-Wen
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Yu, Jui-Yuan
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Yu, Chien-Ying
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Lee, Chen-Yi
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電子工程學系及電子研究所
This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5x of state-of-the-art systems). This chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 W.
A 0.5V 4.85Mbps Dual-Mode Baseband Transceiver with Extended Frequency Calibration for Biotelemetry Applications
(2008)
Yu, Jui-Yuan
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Yu, Chien-Ying
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Huang, Shang-Bin
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Chen, Tsan-Wen
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Chen, Juinn-Ting
This work provides a dual-mode transceiver chipset for wireless body area network (WBAN). The modulation schemes include both MT-CDMA and OFDM. A phase-frequency tunable clock generator (PFTCG) is designed with frequency and phase tuning capability on the fly. A rotator-and-synthesizer driven (RSD) frequency pre-calibration with the aid of the PFTCG enables calibration for extended 100ppm frequency error (2.5x of state-of-the-art systems). This chip is manufactured in 90nm standard CMOS process. The supply voltage to the chip core is globally applied at 0.5V with 12 power- and voltage-domain partitions for sleep-active and voltage-scaling management. The PFTCG is operated at 5MHz with RMS jitter 145ps. The transceiver chipset provides maximum 4.85Mbps data rate with 73.7% power reduction in baseband circuit processing.
A 0.92mm(2) 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Application
(2009)
Yen, Shao-Wei
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Hu, Ming-Chih
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Jou, Shyh-Jye
An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm(2) can achieve 30Mb/s with 23.4mW power consumption.
A 1-100Mb/s 0.5-9.9mW LDPC Convolutional Code Decoder for Body Area Network
(2014)
Chen, Chih-Lung
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Wu, Sheng-Jhan
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1 similar to 100Mb/s with power consumption of 0.5 similar to 9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.
A 1.31Gb/s, 96.6% Utilization Stochastic Nonbinary LDPC Decoder for Small Cell Applications
(2015)
Lee, Xin-Ru
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Yang, Chih-Wen
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.
A 1.69 Gb/s Area-Efficient AES Crypto Core with Compact On-the-fly Key Expansion Unit
(2009)
Liu, Po-Chun
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The AES algorithm published in 2001 is now the most popular symmetric encryption algorithm. Several implementations have beed proposed but few of them considered the hardware cost and the throughput as a whole. This paper presents an AES core to be capable of both encryption and decryption with three different key lengths: 128-, 192-, and 256-bit. The overall hardware cost was optimized by a very compact on-the-fly key expansion unit and a highly integrated encryption/decryption datapath. The compact on-the-fly key expansion unit is achieved by sharing expansion processes of different key lengths. The integrated data datapath shares hardware resources between encryption and decryption. After manufactured in 90nm CMOS technology, the area of the chip is 15,577 equivalent gates with throughput up to 1.69 Gb/s operating at 131.8 MHz.
A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
(2018-01-01)
Ku, Fang-Ju
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Wu, Tung-Yu
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Liao, Yen-Chin
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Chang, Hsie-Chia
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Wong, Wing Hung
This paper presents an implementation of an energy efficient hit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-Hag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm IP9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.
A 11.5-Gbps LDPC Decoder Based on CP-PEG Code Construction
(2009)
Chen, Chih-Lung
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Lin, Kao-Shou
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Chang, Hsie-Chia
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Fang, Wai-Chi
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Lee, Chen-Yi
In this paper, a LDPC decoder chip based on CPPEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high coderate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 x 1.4 mm(2). The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.
A 125 mu W, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications
(2007-01-01)
Liu, Tsu-Ming
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Lin, Ting-An
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Wang, Sheng-Zen
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Lee, Wen-Ping
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Yang, Jiun-Yan
A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18 mu m one-poly six=metal CMOS technology with an area of 15.21 mm(2). For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 mu W and 108 mu W, respectively, at 1 V supply voltage.
A 2 GOPS Quad-Mean Shift Processor with Early Termination for Machine Learning Applications
(2014-01-01)
Tsai, Chang-Hung
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Lee, Hui-Hsuan
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Yu, Wan-Ju
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Lee, Chen-Yi
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電機工程學系
This paper proposes a 2 GOPS quad-mean shift processor (Q-MSP) architecture for data clustering and machine learning applications. By exploiting the linear approximation approach and early termination mechanism, the proposed algorithm can reduce 70% and 40% computational complexity, respectively. Moreover, 4 mean shift processor cores are integrated into the proposed architecture to support parallel processing to further improve system performance. Implemented in Xilinx Virtex-7 FPGA, this architecture occupies 65k LUTs and 3.3MB block memory to achieve 2 GOPS throughput operated at 125MHz.
A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder
(2012-04-01)
Chen, Chih-Lung
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Lin, Yu-Hsiang
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper presents a (491,3,6) time-varying low-density parity check convolutional code (LDPC-CC) decoder chip. This work combines the algorithm level, node level, and bit level optimizations to achieve over 2 Gb/s throughput with acceptable hardware cost and power. The algorithm level optimization is the on-demand variable node activation scheduling with concealing channel values, which can not only achieve twice faster decoding convergence speed than log-belief propagation (log-BP) algorithm, but also reduce the 17% message storage capacity. The node level optimization duplicates the check node units and variable node units and unfolds the message storage first-in-first-outs (FIFOs) so that the throughput becomes twelve multiplying with clock frequency. In the meantime, the bit level optimization is employed to retime the critical path such that the higher clock frequency can be achieved and message storage size is slightly reduced. Furthermore, a novel hybrid-partitioned FIFO is proposed to provide sufficient memory bandwidth to processing units and alleviate power consumption. With these schemes, a test chip of proposed LDPC-CC decoder has been fabricated in 90 nm CMOS technology with core area of 2.37 x 1.14 mm(2). Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with energy efficiency of 0.024 nJ/bit/proc. Depending on the operation mode, power can be scaled down to 90.2 mW while maintaining 1.58 Gb/s at 0.8 V supply.
A 2.4-Gsample/s DVFS FFT processor for MIMO OFDM communication systems
(2008-05-01)
Chen, Yuan
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Lin, Yu-Wei
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Tsao, Yu-Chi
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-2(4) FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FITT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 x 1.88 mm(2). The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner.
A 2.56 Gb/s Soft RS (255,239) Decoder Chip for Optical Communication Systems
(2014-07-01)
Lin, Yi-Min
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Hsu, Chih-Hsiang
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
Due to high transmission rate requirement for optical communication systems, the growing uncertainty of received signals results in the limited transmission distance. In this paper, a decision-confined soft RS decoder chip is proposed to enhance the error correcting performance with area-efficient architectures. Instead of generating numerous possible candidate codewords and determining the most likely one as output codeword, our approach produces only one codeword by confining the degree of error location polynomial. Therefore, hardware complexity is significantly reduced by eliminating decision making unit. Moreover, an iteration-reduced RiBM algorithm is provided to enlarge the coding gain by using more least reliable positions (LRPs) in the limited operation latency. According to simulation results, our proposed soft RS (255, 239; 8) decoder with 5 LRPs outperforms 0.4 dB at 10(-4) codeword error rate (CER) as compared to hard RS decoders. Implemented in standard CMOS 90 nm technology, the soft decoder chip can achieve 2.56 Gb/s throughput with similar complexity as a hard decoder. It can fit well for 10-40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.
A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
(2010-11-01)
Lin, Yi-Min
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Bjorck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.
A 26.9K 314.5Mbps Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
(2009)
Lin, Yi-Min
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Borck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.
A 3.3V 15.6b 6.1pJ/0.02% RH with 10ms Response Humidity Sensor for Respiratory Monitoring
(2014)
Lai, Kelvin Yi-Tse
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Yang, Yu-Tao
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Chen, Bang-Jing
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Shen, Chun-Jen
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Shiu, Ming-Feng
An event-driven and energy-efficient humidity sensor for environment detection and healthcare monitoring is presented. A differential CMOS-MEMS humidity device and proportion-based capacitance-to-digit readout circuit are proposed to overcome PVT variations, and in the meantime to improve sensitivity, response time, and conversion energy. This chip achieves 15.6b 20-90 % RH at 1KS/s, 6.1pJ per 0.02% RH of sensitivity, and 10ms fast response time in TSMC 0.35-mu m CMOS MEMS process. With variations in temperature and voltage, our proposal can minimize the errors from 40% RH to 0.2% RH and 50% RH to 0.1% RH, making it very suitable for wearable respiratory monitoring.
A 3.40ms/GF(p(521)) and 2.77ms/GF(2(521)) DF-ECC Processor with Side-Channel Attack Resistance
(2013-01-01)
Lee, Jen-Wei
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Chung, Szu-Chi
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Chang, Hsie-Chia
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Lee, Chen-Yi
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