Browsing by Author "Lee, Chieh-Jui"

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Agglomerative-Based Flip-Flop Merging and Relocation for Signal Wirelength and Clock Tree Optimization
(2013-07-01)
Liu, Sean Shih-Ying
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Lo, Wan-Ting
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Lee, Chieh-Jui
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Chen, Hung-Ming
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電子工程學系及電子研究所
In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all aspects, including number of flip-flop reductions, increase in signal wirelength, displacement of flip-flops, and execution time. Our proposed algorithm also has minimal disruption to original placement. In comparison with Jiang et al. [2011], Wang et al. [2011], and Chang et al. [2010], our proposed algorithm has the least displacement when relocating merged flip-flops. While previous works on flip-flop merging focus on the number of flip-flop reduction, we further evaluate the power consumption of clock tree after flip-flop merging. To further minimize clock tree wirelength, we propose a framework that determines a preferable location for relocated merged flip-flops for clock tree synthesis (CTS). Experimental results show that our CTS-driven flip-flop merging can reduce clock tree wirelength by an average of 7.82% with minimum clock network power consumption compared to all of the previous works.
Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization
(2012-01-01)
Liu, Sean Shih-Ying
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Lee, Chieh-Jui
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, an optimization methodology using agglomerative-based clustering for number of flip-flop reduction and signal wirelength minimization is proposed. Comparing to previous works on flip-flop reduction, our method can obtain an optimal tradeoff curve between flip-flop number reduction and increase in signal wirelength. Our proposed methodology outperforms [1] and [12] in both reducing number of flip-flops and minimizing increase in signal wirelength. In comparison with [9], our methodology obtains a tradeoff of 15.8% reduction in flip-flop's signal wirelength with 16.9%additional flip-flops. Due to the nature of agglomerative clustering, when relocating flip-flops, our proposed method minimizes total displacement by an average of 5.9%, 8.0%, 181.4% in comparison with [12], [1] and [9] respectively.
Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming
(2013-01-01)
Liu, Sean Shih-Ying
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Lee, Chieh-Jui
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Huang, Chuan-Chia
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Chen, Hung-Ming
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Lin, Chang-Tzu
In this paper, we propose a framework that automatically generates a power network based on given placed design and verifies the power network by the commercial tool without IR and Electro-Migration (EM) violations. Our framework integrates synthesis, optimization and analysis of power network. A deterministic method is proposed to decide number and location of power stripes based on clustering analysis. After an initial power network is synthesized, we propose a sensitivity matrix G(s) which is the correlation between updates in stripe resistance and nodal voltage. An optimization scheme based on Sequential Linear Programming (SLP) is applied to iteratively adjust power network to satisfy a given IR drop constraint. The proposed framework constantly updates voltage distribution in response to incremental change in power network. To accurately capture voltage distribution on a given chip, our power network models every existing power stripes and via resistances on each layer. Experimental result demonstrates that our power network analysis can accurately capture voltage distribution on a given chip and effectively minimize power network area. The proposed methodology is experimented on two real designs in TSMC 90nm and UMC 90nm technology respectively and achieves 9%-32% reduction in power network area, compared with the results from modern commercial PG synthesizer.
Hierarchical Power Network Synthesis for Multiple Power Domain Designs
(2012)
Lee, Chieh-Jui
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Liu, Sean Shih-Ying
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Huang, Chuan-Chia
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Chen, Hung-Ming
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Lin, Chang-Tzu
In this paper, we propose a methodology that synthesize and optimize the power network for design with multiple power domains. An architecture is presented to represent the power network with presence of sleep transistors. The power network is numerically modeled to RC network using Modified Nodal Analysis and solved using Conjugate Gradient Method. Regarding to IR drop effect mitigation, an optimization technique is proposed based on Simulated Annealing that minimize total power stripe area while satisfying a given IR drop constraint. In consideration of multiple power domains, the given power domains are represented in tree-like structure and our algorithm is recursively applied to synthesize and optimize the power network for each power domain in a hierarchical fashion. The proposed methodology is integrated to commercial design tool and experimented on real design case for evaluation. To ensure practical aspect of our approach, evaluation is performed on latest digital design commercial tool. Design data and parameters are extracted using Open Access. The result of our algorithm is fed back to latest commercial tool for final IR and EM analysis. Our algorithm is tested on both industrial testcase and academic MCNC benchmark. Comparing to conventional P/G network, using our power network synthesis can achieve 31% - 35% reduction in total P/G area while satisfying maximum 10% IR-drop constraint.
Improving Power Delivery Network Design by Practical Methodologies
(2014-01-01)
Huang, Chia-Chi
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Lin, Chang-Tzu
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Liao, Wei-Syun
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Lee, Chieh-Jui
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Chen, Hung-Ming
There are many works on the power network design and prototyping for digital designs, however some usual and practical design concerns are not addressed. In this work, we present a realistic power network design methodology without IR violation certified by state-of-the-art commercial tool. Our work integrates analysis, optimization and synthesis of power network. In particular, we consider thermal effect and power pad\'s positions during the prototyping of power network. A scenario in placement regarding the violation of design rules is considered and resolved by maximum flow algorithm at the same stage. After the synthesis of initial power network, we generate a sensitivity matrix which is correlated with nodal voltage and resistances of net and via in metal layers. Furthermore, a Sequential Linear Programming(SLP) will be applied to adjust the sensitivity matrix iteratively until the IR drop constraint is satisfied. Our work is experimented on a real design in TSMC 65nm LP process, and the result validates our framework that the IR-Drop can be reduced to 2% of supply voltage.