Browsing by Author "Lee, Chiou-Yng"

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Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm
(2016)
Yuan, Shyan-Ming
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Lee, Chiou-Yng
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Fan, Chia-Chen
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資訊工程學系
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Department of Computer Science
This paper presents a efficient digit-serial GF(2m) multiplier. The proposed architecture using digit-serial of concept to combine the principle of Karatsuba multiplier which can reduce circuit space complexity, also it is suitable for Elliptic Curve Cryptography (ECC) technology. We knows that the password system\'s operation core is a multiplier, however that password system\'s multiplier is very big, so it is necessary for reduce the area and time\'s complexity. This paper is implement three smaller multiplier and digit-serial in FPGA to reduce time and area complexity. This method uses 3dm/2 AND gate, 6 m + n+ 3dm/2 + m/2 + d-7 XORs and 3 m-3 registers. The paper using Altera FPGA Quartus II to simulate four different multipliers, 36 x 36, 84 x 84, 126 x 126 and 204 x 204, and implemented on Cyclone II EP2C70F896C8 experimental platform. The experimental results show that the proposed multipliers have lower time complexity than the existing digit-serial structures. The proposed architecture can reduce the time x space complexity decreasing when the bit-size of multiplier is increasing.
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field
(2018-01-01)
Lee, Chiou-Yng
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Fan, Chia-Chen
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Xie, Jiafeng
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Yuan, Shyan-Ming
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資訊工程學系
Three-operation multiplication (TOM) over binary extension field is frequently encountered in cryptosystems such as elliptic curve cryptography. Though digit-serial polynomial basis multipliers are usually preferred for the realization of TOM due to their efficient tradeoff in implementation complexity, the Karatsuba algorithm (KA)-based strategy is rarely employed to reduce the complexity further. Based on this reason, in this paper, we derive a novel low-complexity implementation of TOM based on a new KA-based digit-serial multiplier. The proposed TOM is obtained through two novel coherent interdependent efforts: 1) mapping an efficient KA-based algorithm into a novel digit-serial multiplier and 2) obtaining a new TOM structure through the novel derivation of the TOM algorithm. From the estimated results, it is shown that the proposed structure has significant lower area-time-complexities when compared with the existing competing TOMs. The proposed TOM is highly regular with low-complexity, and hence can be employed in many cryptographic applications.
Low-Complexity Digit-Serial Multiplier Over GF(2(m)) Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition
(2017-02)
Lee, Chiou-Yng
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Meher, Pramod Kumar
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Fan, Chia-Chen
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Yuan, Shyan-Ming
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資訊工程學系
In this paper, we have shown that a regular Toeplitz matrix-vector product (TMVP) can be transformed into a Toeplitz block TMVP (TBTMVP) using a suitable permutation matrix. Based on the TBTMVP representation, we have proposed a new (a, b)-way TBTMVP decomposition algorithm for implementing a digit-serial multiplication. Moreover, it is shown that, based on iterative block recombination, we can improve the space complexity of the proposed TBTMVP decomposition. From the synthesis results, we have shown that the proposed TBTMVP-based multiplier involves less area, less area-delay product, and higher throughput compared with the existing digitserial multipliers.
New Digit-Serial Three-Operand Multiplier over Binary Extension Fields for High-Performance Applications
(2017-01-01)
Lee, Chiou-Yng
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Fan, Chia-Chen
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Yuan, Shyan-Ming
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交大名義發表
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National Chiao Tung University
Digit-serial polynomial basis multipliers over GF(2(m)) are broadly applied in elliptic curve cryptography, because squaring and polynomial reduction in GF(2(m)) are simple operations. In this paper, we define a partial product formula to derive a new digit-serial three-operand multiplication algorithm. On the basis of the proposed algorithm, we have derived a new digit-serial structures for computing three-operand multiplication. Our proposed structures can reduce latency (clock cycles) by approximately 50% compared to the existing digit-serial two-operand multipliers used to perform three-operand multiplication. Therefore, the proposed structure can achieve high-throughput designs. According to the analysis reports, the advantages of the proposed designs are a short critical path, a low area-delay product, and a high throughput.