Browsing by Author "Lee, Chung Len"

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A fast two-stage sample-and-hold amplifier for pipelined ADC application
(2008)
Ruan, Jian
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Lee, Chung Len
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a differential input, two-stage structure sample-hold-amplifier (SHA) for which each stage can be designed and adjusted separately to have a large input dynamic range and fast operation speed. The clock feed through and charge injection is eliminated. The implemented SHA with a 0.18um 1.8V process shows that it can sample a 2.5 MHz signal at 40 MHz with a 63d8 SFDR and a -62 dB THD which is able to realize an ADC of 10 bit resolution.
A multilayer data copy scheme for low cost test with controlled scan-in power for multiple scan chain designs
(2006)
Lin, Shih Ping
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Lee, Chung Len
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Chen, Jwu E.
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Chen, Ji-Jan
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Luo, Kun-Lun
The random-like filling strategy pursuing high compression for scan test introduces large test power. To pursue high compression in conjunction with reducing test power for multiple scan chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a Multilayer Data Copy (MDC) scheme for test compression as well as test power reduction for multiple scan designs. The scheme utilizes a buffer, which supports fast load using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied ATPG-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with little area design overhead.
Arbitrary waveform generator based on direct digital frequency synthesizer
(2008)
Hu, Weibo
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Lee, Chung Len
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Wang, Xin\'an
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Arbitrary Waveform Generator (AWG) is an important signal generation module in many applications such as communication and mixed signal testing. This paper describes an AWG based on Direct Digital Frequency Synthesizer (FFDS). The CORDIC algorithm with an iterative process and a pipeline plus parallel structure are used to implement the AWG whose frequencies and amplitudes of sinusoid waveforms in the arbitrary wave can be controlled by frequency control words (FCWs), initial vectors of CORDIC module respectively. Compared to the conventional AWG, it is flexible and saves much hardware.
Electrical and reliability improvement in polyoxide by fluorine implantation
(2007)
Kao, Chyuan Haur
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Lai, Chao Sung
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Lee, Chung Len
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We show that the incorporation of fluorine into the oxide grown on polysilicon (polyoxide) not only improves the electrical characteristics (i.e., lower leakage current, higher electrical breakdown field), but also improves the reliability (lower electron trapping rate, larger Q(bd)). This improvement is believed to be due to the stress relaxation of the polyoxide and smoother polysilicon/polyoxide interface by the fluorine incorporation. The optimum fluorine dose (2x10(14)) shows the best characteristics such as E-bd over 12 MV/cm and Q(bd)similar to 2 C/cm(2). However, excessive fluorination (1x10(15)) seems to result in performance degradation due to the generation of nonbridging oxygen centers. (c) 2007 The Electrochemical Society.
Nitrogen effects on the integrity of silicon dioxide grown on polycrystalline silicon
(2007)
Lai, Chao Sung
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Kao, Chyuan Haur
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Lee, Chung Len
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Lei, Tan Fu
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電子工程學系及電子研究所
In this paper, we describe a simple technique to achieve a thin nitrided polyoxide film, only requiring an extra nitrogen implantation to be compatible with the floating gate nonvolatile memory process. The integrity of polyoxides is improved by using the through-silicon-gate nitrogen implantation. Nitridation can be achieved by implanting nitrogen into polysilicon gate followed by a high temperature annealing to drive the nitrogen atoms across the polysilicon, through the polyoxide, and to incorporate nitrogen at the polyoxide/polysilicon interface. The nitrogen-rich layer formed during the driven-in process not only strengthens the polyoxide structure but also improves the polyoxide quality. Improvements of electrical characteristics such as a low leakage current, a low electron trapping, and a high breakdown field for both positive and negative biases have been observed. (c) 2007 The Electrochemical Society.
Oscillation ring based interconnect test scheme for SOC
(2005)
Li, Katherine Shu-Min
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Lee, Chung Len
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Su, Chauchin
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Chen, Jwu E.
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電子工程學系及電子研究所
We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.
Polarity asymmetry of polyoxide grown on phosphorus in situ doped polysilicon
(2006)
Kao, Chyuan Haur
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Lai, Chao Sung
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Lee, Chung Len
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We show that polyoxides grown on phosphorus in situ doped polysilicon have larger polarity asymmetry than that on the POCl3-doped polysilicon. It may be not only the surface roughness between the polysilicon/polyoxide interfaces, but also the phosphorus distribution in the interfaces. For the phosphorus in situ doped poly film, the phosphorus piled up at the poly-1/polyoxide interface should result from the out-diffusion of the poly-1 doping during the tetraethyl orthosilicate oxide deposition process. However, the phosphorus concentration near the polyoxide/top poly-2 interface was lower than the bulk concentration of the polysilicon film, which may result from insufficient phosphorus concentration near the polyoxide/top poly-2 interface without subsequent annealing and dopant activation. Therefore, this may affect the polarity asymmetry of the electrical characteristics for the phosphorus in situ doped samples. Especially, the thermal polyoxide had the largest polarity asymmetry due to very high phosphorus concentration piled up in the bottom poly-1/polyoxide interface. We also show that the top poly-2 doping process affects the phosphorus distribution in the polysilicon/polyoxide interfaces, and further, affects the polyoxide performance.