Browsing by Author "Lee, Chung-Len"

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A multilayer data copy test data com pression scheme for reducing shifting-in power for multiple scan design
(2007-07-01)
Lin, Shih-Ping
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Lee, Chung-Len
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Chen, Jwu-E
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Chen, Ji-Jan
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Luo, Kun-Lun
The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works Were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes,a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.
A reconfigurable MAC architecture implemented with mixed-V(t) standard cell library
(2008)
Wang, Li-Rong
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Chiu, Yi-Wei
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Hu, Chia-Lin
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Tu, Ming-Hsien
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Jou, Shyh-Jye
In this paper, a 32-bit reconfigurable multiplication-accumulation architecture, which can execute flexibly one 32x32, two 16x16 or four 8x8 two's complement multiply-accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-V(t) CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design.
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus
(2009-02-01)
Li, Katherine Shu-Min
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Lee, Chung-Len
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Su, Chauchin
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Chen, Jwu E.
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電子工程學系及電子研究所
For very deep sub-micrometer VLSI, crosstalk becomes an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.
A well-structured modified Booth multiplier design
(2008)
Wang, Li-Rong
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Jou, Shyh-Jye
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Lee, Chung-Len
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a well-structured modified Booth encoding (MBE) multiplier architecture. The design adopts an improved Booth encoder and selector to achieve an extra-row-removal and a hybrid spare-tree approach to design two's complementation circuit to both reduce the area and improve the speed. Experimental results on a 32 bit multiplier show that it obtains area and power savings of 15.8% and 11.7% respectively over the classical design and of 7.5% and 5.5% respectively over the design of the best performance reported so far.
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
(2006-11-01)
Li, Katherine Shu-Min
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Su, Chauchin
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Chang, Yao-Wen
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Lee, Chung-Len
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Chen, Jwu E.
An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution.
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
(2006-01-01)
Li, Katherine Shu-Min
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Chang, Yao-Wen
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Su, Chauchin
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Lee, Chung-Len
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Chen, Jwu E.
We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and crosstalk glitches. We analyze the diagnosability of an interconnect structure and propose a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm which achieves the optimal diagnosability. Two optimization techniques improve the efficiency and effectiveness of interconnect diagnosis. In all experiments, our method achieves 100% fault coverage and the optimal diagnosis resolution.
IEEE standard 1500 compatible oscillation ring test methodology for interconnect delay and crosstalk detection
(2007-08-01)
Li, Katherine Shu-Min
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Lee, Chung-Len
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Su, Chauchin
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Chen, Jwu E.
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電子工程學系及電子研究所
A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.
Multilevel full-chip routing with testability and yield enhancement
(2007-09-01)
Li, Katherine Shu-Min
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Chang, Yao-Wen
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Lee, Chung-Len
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Sul, Chauchin
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Chen, Jwu E.
We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme for interconnects based on the popular IEEE Standard 1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. 2) We present a heuristic to reduce routing congestion to optimize the multiple-fault probability, chemical-mechanical polishing- and optical proximity correction-induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the Microelectronics Center for North Carolina benchmark circuits show that the proposed ORT method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects. Further, the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion.
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design
(2011-06-01)
Wang, Li-Rong
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Tu, Ming-Hsien
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Jou, Shyh-Jye
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Lee, Chung-Len
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電機工程學系
This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 32 x 32, two 16 x 16 or four 8 x 8 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-V(t) standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V(t) standard cell library.