Browsing by Author "Lee, Da-Yuan"

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Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET
(2008-11-01)
Liu, Po-Tsun
;
Huang, Chen-Shuo
;
Lim, Peng-Soon
;
Lee, Da-Yuan
;
Tsao, Shueh-Wen
Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.
Novel Silicon Surface Pre-Treatment (SSPT) technique for CMOS device performance boosting
(2008-01-01)
Lee, Da-Yuan
;
Chen, C. C.
;
Huang, C. H.
;
Lim, P. S.
;
Chan, M. H.
In this paper, a novel surface treatment technique using Silicon Surface Pre-Treatment (SSPT) technique to boost high performance CMOS circuit is reported. This approach provides a smooth silicon surface and extends the effective channel width to enhance device performance on both N and PMOSFET. In this work, a smooth and rounded active area (AA) surface was successfully fabricated. Using this technique, we demonstrated a significant device boost of 15% and 7% on small dimension N and PMOSFET, respectively. These achievements were demonstrated without negative impact on GOI and NBTI.