Browsing by Author "Lee, Geeng-Wei"

Now showing 1 - 4 of 4

A precise bandwidth control arbitration algorithm for hard real-time SoC buses
(2007)
Lin, Bu-Ching
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Lee, Geeng-Wei
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Huang, Juinn-Dar
;
Jou, Jing-Yang
;
電子工程學系及電子研究所
On an SoC bus, contentions occur while different IP cores request the bus access at the same time. Hence an arbiter is mandatory to deal with the contention issue on a shared bus system. In different applications, IPs may have real-time and/or bandwidth requirements. It is very difficult to design an arbitration algorithm to simultaneously meet these two requirements. In this paper, we propose an innovative arbitration algorithm, RB-lottery, to meet both of the requirements. It can provide not only the hard real-time guarantee but also the precise bandwidth controllability. The experimental results show that RB-lottery outperforms several well-known existing arbitration algorithms.
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication
(2006)
Chen, Chien-Hua
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Lee, Geeng-Wei
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Huang, Juinn-Dar
;
Jou, Jing-Yang
;
電子工程學系及電子研究所
In shared SoC bus systems, arbiters are usually adopted to solve bus contentions with various kinds of arbitration algorithms. We propose an arbitration algorithm, RT lottery, which is designed to meet both hard real-time and bandwidth requirements. For fast evaluation and exploration, we use high abstract-level models in our system simulation environment to generate parameters for our configurable arbiter. The experimental results show that RT-lottery can meet all hard real-time requirements and perform very well in bandwidth allocation. The results also show that RT-lottery outperforms several commonly-used arbitration algorithms today.
Fine-grained bandwidth control arbiter and the method thereof
(2008-08-28)
Huang, Juinn-Dar
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Lin, Bu-Ching
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Lee, Geeng-Wei
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Jou, Jing-Yang
A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.
Verification of pin-accurate port connections
(2008-09-01)
Lee, Geeng-Wei
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Huang, Juinn-Dar
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Wang, Chun-Yao
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Jou, Jing-Yang
;
電子工程學系及電子研究所
Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow.