Browsing by Author "Lee, Huang-Chang"

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A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications
(2014-09-01)
Cheng, Chung-Chao
;
Yang, Jeng-Da
;
Lee, Huang-Chang
;
Yang, Chia-Hsiang
;
Ueng, Yeong-Luh
This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. An early termination scheme is proposed in order to prevent unnecessary energy dissipation for both low and high signal-to-noise-ratio regions. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz, achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance.
An Iterative Soft-decision Decoding Algorithm for Reed-Solomon Codes
(2017-01-01)
Lee, Huang-Chang
;
Wu, Jyun-Han
;
Wang, Chung-Hsuan
;
Ueng, Yeong-Luh
;
電機工程學系
This paper proposes an iterative soft-decision decoding algorithm for Reed-Solomon (RS) codes. The proposed decoding algorithm combines the concepts of adapting the parity-check matrix and informed dynamic scheduling decoding. The parity-check matrix is re-arranged before each iteration, where the systematic part is mapped to the least reliable bits, consequently reducing their influence on the other bits. Using dynamic scheduling, the more important decoding messages are updated to these least reliable bits, meaning that the majority of the error bits with low reliability can be corrected. When the proposed integrated decoding is applied to (255, 239) RS code, the difference between its frame error rate performance (FER) and the maximum-likelihood (ML) bound can be reduced to 0.8 dB, and a gain of about 0.1 dB is achieved compared to all the previously recorded soft-decision decoding for RS codes.
Iterative Soft-decision Decoding of Reed-Solomon Codes Using Informed Dynamic Scheduling
(2015)
Lee, Huang-Chang
;
Huang, Guan-Xuan
;
Wang, Chung-Hsuan
;
Ueng, Yeong-Luh
;
傳播研究所
In this paper, an iterative soft-decision decoding algorithm is proposed for Reed-Solomon (RS) codes. The proposed decoding algorithm combines the concepts of adapting the parity-check matrix and informed dynamic scheduling. Before each iteration, the parity-check matrix is re-arranged according to the reliability of the codeword bits, meaning that the influence of the least reliable variable nodes on the decoding process can be reduced. Consequently, the important decoding messages can be scheduled to be updated first, and the reliability of the least reliable bits can be enhanced. The simulation results show that the proposed decoding algorithm can provide significant improvement in the error-rate performance. By using the proposed algorithm, a gain of 0.5 dB can be achieved compared to the conventional adapting belief propagation algorithm.