Browsing by Author "Lee, J. H."

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Cycle time estimation for semiconductor final testing processes with Weibull-distributed waiting time
(2012)
Tai, Y. T.
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Pearn, W. L.
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Lee, J. H.
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工業工程與管理學系
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Department of Industrial Engineering and Management
Accurate cycle time is an essential planning basis required for many production applications, especially on due date commitments, performance metrics analysing, capacity planning, and scheduling. The re-entrant final testing process is the final stage of the complicated semiconductor manufacturing process. To enhance the ability of quick responses and to achieve better on-time delivery in final testing factories, it is essential to develop an accurate cycle time estimation method. In this paper, we provide a statistical approach to calculate the cycle time for multi-layer semiconductor final testing involving the sum of multiple Weibull-distributed waiting times. In addition, percentiles of the cycle time are obtained which are useful to industrial practitioners for due date commitments satisfying the targeted on-time delivery rate. To demonstrate the applicability of the proposed cycle time estimation model, a real example in a semiconductor final testing factory which is located on the Science-based Industrial Park in Hsinchu, Taiwan, is presented.
Statistical Approach for Cycle Time Estimation in Semiconductor Packaging Factories
(2009-07-01)
Pearn, W. L.
;
Tai, Yu-Ting
;
Lee, J. H.
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
In the semiconductor industry, to enhance customer satisfactions and ability of quick responses, the development of cycle time estimation model is very important. Cycle time estimation is an essential planning basis, which has many applications, especially on the analyses of performance indexes, capacity planning, and the assignments of due dates. In this paper, we provide a statistical approach for cycle time estimation in semiconductor plastic ball grid array (PBGA) packaging factories. Due to today's fierce competitive environments in the semiconductor industry, planners involved in PBGA packaging factories need an approach to obtain estimated cycle times with different confidence to ensure the due date assignments more accurately. Therefore, upper confidence bounds of estimated cycle times at various confidence coefficients are also presented in this paper. We demonstrate the applicability of the proposed cycle time estimation model incorporating the upper confidence bounds by presenting a real-world example taken from a PBGA packaging shop floor in a semiconductor packaging factory located in the Science-Based Industrial Park in Hsinchu, Taiwan.