Browsing by Author "Lee, Jam-Wem"

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A compact model for electrostatic discharge protection nanoelectronics simulation
(2005)
Chou, Hung-Mu
;
Yu, Shao-Ming
;
Lee, Jam-Wem
;
Li, Yiming
;
電信工程研究所
In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.
A reliability model for low-temperature polycrystalline silicon thin-film transistors
(2007-05-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Lee, Po-Hao
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We proposed here a reliability model that successfully. introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.
Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors
(2007)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
The degradation mechanisms of both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation. (c) 2007 The Electrochemical Society.
Enhanced performance and reliability for solid phase crystallized poly-Si TFTs with argon ion implantation
(2007)
Chang, Chia-Wen
;
Chang, Che-Lun
;
Luo, Wun-Chen
;
Lee, Jam-Wem
;
Lei, Tan-Fu
Performance and reliability improvement for polycrystalline silicon thin-film transistors (poly-Si TFrs) with Argon ion implantation are proposed for the first time. By adopting this novel surface -nucleation solid -phase-cry stallization scheme, not only the grain size of poly-Si can be increased but also the intragranular defects can be suppressed effectively. Therefore, a high quality of poly-Si film in channel with better crystallinity is formed. Argon-implanted TFrs have been successfully fabricated and the experimental results demonstrate a superior field-effect mobility of 46. 06 cm(2)/VS, a fewer grain boundary trap density of 3.44 x 10(12) cm(-2) than those of conventional TFrs. The novel proposed structure is a very promising candidate for the future high-performance large-area device applications.
Improvement of electrical characteristics for novel process-compatible floating channel solid-phase crystallized poly-Si TFTs
(2007)
Chang, Chia-Wen
;
Chang, Che-Lun
;
Lee, Jam-Wem
;
Lei, Tan-Fu
;
電子工程學系及電子研究所
High-performance polycrystalline-silicon thin-film transistors (poly-Si TFTs) with floating channel solid-phase crystallization are proposed for the first time. By adopting this novel crystallization scheme, a better crystalline poly-Si film can be obtained in the suspended channel film. Poly-Si TFTs with this novel floating channel structure have been successfully fabricated and the experimental results demonstrate a superior electrical performance and reliability.
Performance and reliability improvement for poly-Si TFTs using fluorinated silicate glass inter-layer-dielectric passivation
(2007)
Chang, Chia-Wen
;
Wu, Tin-Wei
;
Wang, Tong-Yi
;
Chang, Che-Lun
;
Lee, Jam-Wem
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with fluorinated silicate glass (FSG) inter-layer dielectric (ILD) passivation layer were proposed and demonstrated in this study. The presence of outdiffused fluorine atoms from FSG layer can eliminate Si dangling bonds at the grain boundaries near the drain side. The proposed short channel poly-Si TFTs with FSG ILD passivation have a slightly improved on-current, a obviously suppressed serious kink-effect, and a remarkably reduced off-leakage current than those with undoped SiO2 ILD passivation. Furthermore, the incorporation of fluorine atoms in poly-Si film can also form stronger Si-F bonds at drain side to enhance the immunity to hot carrier stress. Besides, the proposed TFTs structure is simple, low cost, and process compatible with present TFTs manufacturing technology.
Plasma damage-enhanced negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors
(2006-11-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Chen, Wei-g Chen
;
Lin, Hsiao-Yi
;
Yeh, Kuan-Lin
In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in UPS TFTs. That is, when performing the NBTI measurement, the UPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the UPS TFT circuitry design.
Plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors
(2007)
Chen, Chih-Yang
;
Wang, Shen-De
;
Shieh, Ming-Shan
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We have investigated the impact of plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The LTPS TFTs having different antenna structures were used to study the effects of the plasma-etching process. We observed that performance instability occurred for the devices having a relatively large-area antenna. Plasma damage mainly caused nonuniform distribution of the threshold voltages in the LTPS TFTs, presumably because of charge trapping in the gate dielectric during the plasma-etching process. The reliabilities of the LTPS TFTs having larger antenna areas were found to be more degraded under gate-bias stress and hot-carrier stress than those of the samples having smaller antenna areas. Because of their enhanced plasma damage, we speculate that the LTPS TFTs having larger antenna areas possess more trap states in the gate dielectrics. During gate-bias stress or hot-carrier stress, therefore, charges can be injected into the gate dielectric through trap-assisted tunneling, resulting in significant degradation of both the performance and reliability. (c) 2006 The Electrochemical Society.
Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors
(2004-10-01)
Li, Yiming
;
Lee, Jam-Wem
;
Chou, Hung-Mu
;
電子物理學系
;
友訊交大聯合研發中心
In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (RSiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (similar to 8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (V-t), the drain induced barrier height lowering (DIBL), and the gate capacitance (C-G) are estimated with respect to different gate length (L-G), gate bias (V-G), and R-SiGe. For short channel effects, such as V-t roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one.