Browsing by Author "Lee, Jam-Wen"

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A floating gate design for electrostatic discharge protection circuits
(2007-02-01)
Chou, Hung-Mu
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Lee, Jam-Wen
;
Li, Yiming
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電信工程研究所
;
友訊交大聯合研發中心
In this paper, a circuit design method for electrostatic discharge (ESD) protection is presented. It considers the gate floating state for ESD protection and negatively gate biased for leakage suppression under normal operations. The circuit is achieved by adding a switch device and a negatively biased circuit at the gate of ESD protection devices. Robustness and leakage of ESD protection circuit are improved. The circuit suits thin thickness of gate oxide of complementary metal oxide semiconductor (CMOS) devices due to an elimination of oxide damage. This approach benefits design of very large-scaled integration circuit and implementation of system-on-chip with sub-100 nm CMOS devices. (c) 2006 Elsevier B.V. All rights reserved.
An optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuit
(2007-02-01)
Yu, Shao-Ming
;
Lee, Jam-Wen
;
Li, Yiming
;
資訊工程學系
;
電信工程研究所
In this paper we propose a silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS devices. According to our practical implementation, it is found that a comprehensive silicide optimization can be achieved on the gate, drain, and source sides with very few testkey designs. Our study shows that there is a high characteristic efficiency for various conditions in particular, for optimizing the performance of sub-100 nm complementary metal-oxide-semiconductor devices in system-on-a-chip era. (c) 2006 Elsevier B.V. All rights reserved.
Process induced instability and reliability issues in low temperature poly-Si thin film transistors
(2006)
Chen, Chih-Yang
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Wang, Shen-De
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Shieh, Ming-Shan
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Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We investigated the impact of plasma process on the devices' performance and reliability degradation of low temperature poly-Si thin film transistors (LTPS TFTs). LTPS TFTs with different antenna areas were used to study the effects of the plasma etching process on the devices. The larger TFT antenna area, the more performance instability occurs. The reliability of LTPS TFTs with large antenna areas was found to be degraded from gate bias stress and hot carrier stress.