Browsing by Author "Lee, Jenq-Kuen"

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Analyzing OpenCL 2.0 Workloads Using a Heterogeneous CPU-GPU Simulator
(2017-01-01)
Wang, Li
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Tsai, Ren-Wei
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Wang, Shao-Chung
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Chen, Kun-Chih
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Wang, Po-Han
Heterogeneous CPU-GPU systems have recently emerged as an energy-efficient computing platform. A robust integrated CPU-GPU simulator is essential to facilitate researches in this direction. While few integrated CPU-GPU simulators are available, similar tools that support OpenCL 2.0, a widely used new standard with promising heterogeneous computing features, are currently missing. In this paper, we extend the existing integrated CPU-GPU simulator, gem5-gpu, to support OpenCL 2.0. In addition, we conduct experiments on the extended simulator to see the impact of new features introduced by OpenCL 2.0. Our OpenCL 2.0 compatible simulator is successfully validated against a state-of-the-art commercial product, and is expected to help boost future studies in heterogeneous CPU-GPU systems.
On the And-Or-Scheduling Problems
(2014)
Yang, Wuu
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Huang, Ming-Hsiang
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Lee, Jenq-Kuen
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資訊工程學系
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Department of Computer Science
In the and-or scheduling model, a project consists of several tasks. Each task has a duration attribute. A task can be performed only when all of its requirements are satisfied. After a task is completed, more requirements become satisfied. A characteristic of the AOscheduling projects is that a requirement may be satisfied in several ways. Several questions concerning AOscheduling might be interesting, including whether the project can be completed, the earliest time a project can be completed, the minimal number of processors needed to complete the project, and assigning tasks to processors, etc. We use Petri nets and segment graphs to analyze AOscheduling projects.
Optimized Memory Access Support for Data Layout Conversion on Heterogeneous Multi-core Systems
(2014-01-01)
Hsu, Chia-Chen
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Lin, Cheng-Yen
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Chen, Shin Kai
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Liu, Chih-Wei
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Lee, Jenq-Kuen
Heterogeneous multi-core systems that contain multiple CPUs and GPUs are gaining momentum, as they are providing different computation power to meet the performance demand of modern applications. On such systems, developers try to fully utilize the computation power both for CPU and GPU by using the emerging programming models such as CUDA and OpenCL. To achieve the maximal performance, developers must carefully offload the appropriate workload to the compute devices according to the characteristics of target architecture. Under such scenario, seamlessly data motion between different processors become crucial. Additionally, re-organizing the data layout to fit the target architectures, such as array-of-structure (AOS) for CPU, structure-of-array (SOA) for GPU, and coordinate (COO) format to ELLPACK (ELL) for sparse computation, address such concern. In this paper, we propose a hardware memory manager, which efficiently optimizes the conversion of data layouts for heterogeneous multi-core systems on-the-fly. We address coalescing and sparse format conversion issue in our design. A novel ping-pong transpose architecture is devised to reorganize non-coalescing access pattern, and a histogram unit and sparse address generator are presented to process sparse storage format transformation. Our design reduces the overhead of data transfer and layout transformation among CPU and GPU. In our experiment, our design achieves 68.5 to 2.19 times speed up comparing to software-based library depending on data size.
Parallel Architecture Core (PAC)-the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools
(2011-03-01)
Chang, David Chih-Wei
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Lin, Tay-Jyi
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Wu, Chung-Ju
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Lee, Jenq-Kuen
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Chu, Yuan-Hua
In order to develop a low-power and high-performance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. A VLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dual-core PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).
Translating the ARM Neon and VFP instructions in a binary translator
(2016-12)
Guo, Yu-Chuan
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Yang, Wuu
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Chen, Jiunn-Yeu
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Lee, Jenq-Kuen
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交大名義發表
Binary translation attempts to emulate one instruction set with another on the same or different platforms. The important technique is widely used in modern software. Vector and floating-point instructions are widely used in many applications, including multimedia, graphics, and gaming. Although these instructions are usually simulated with software in a binary translator, it is important to support them such that the host single-instruction, multiple-data (SIMD) and floating-point hardware are efficiently used during emulation. We report our design and implementation of the emulation of ARM Neon and vector floating point (VFP) instructions in the machine-code-to-low-level-virtual-machine (MC2LLVM) binary translator. The Neon and VFP instructions are first translated into carefully chosen sequences of LLVM intermediate representation (IR), and later, the IR sequences are optimized and translated into the host native binary by the existing LLVM backend. Because MC2LLVM makes use of the vector and floating-point types in LLVM IR, the generated host native binary can take full advantage of the vector and floating-point functional units, if present, of the host machine. To be fully compliant with Neon and VFP instruction sets, all the features are supported, including the flush-to-zero mode, default not a number mode, and floating-point exceptions. The experimental results show that code generated by MC2LLVM with the Neon and VFP extensions achieves an average speedup of 1.174x in SPEC 2006 benchmark suites and exhibits a floating-point throughput of 12.05x in LINPACK, compared with code generated by MC2LLVM without the Neon and VFP extensions. Furthermore, MC2LLVM is 3.36x faster than QEMU for processing Neon/VFP instructions. Copyright (c) 2016 John Wiley & Sons, Ltd.