Browsing by Author "Lee, Jian-Hsing"

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Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process
(2019-07-01)
Nidhi, Karuna
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Ker, Ming-Dou
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Lee, Jian-Hsing
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Huang, Shao-Chang
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交大名義發表
Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (I-AV) achieved from themodified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 000 mu m.
Energy Transformation Between the Inductor and the Power Transistor for the Unclamped Inductive Switching (UIS) Test
(2020-06-01)
Nidhi, Karuna
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Lee, Jian-Hsing
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Huang, Shao-Chang
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Ker, Ming-Dou
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交大名義發表
The fundamental model of energy transformation between the inductor and the power transistor for the unclamped inductive switching (UIS) test is inspected. Based on the experimental results, the energy stored in the inductor at the period of the channel turn-on can be dissipated by the power transistor after the channel is turned off. In this work, a new theoretical model to well describe the electrical and thermal behaviors of the power transistor during the unclamped inductive switching (UIS) test has been identified and analyzed with the experimental silicon results under different inductor values in 0.15 mu m BCD process. The total UIS energy reduced due to series resistance of the inductor and the power transistor has been theoretically explained and well matches with the experimental measured results on silicon.
Improving Safe-Operating-Area o f a 5-V n-Channel Large Array MOSFET in a 0.15-mu m BCD Process
(2018-07-01)
Nidhi, Karuna
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Ker, Ming-Dou
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Lin, Tingyou
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Lee, Jian-Hsing
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資訊工程學系
The safe-operating-area (SOA) of large array device (LAD) is one of the most important factors affecting the device reliability. In this paper, the improvement of the electrical-SOA (E-SOA) and the thermal-SOA (T-SOA) by using an optional implantation layer for 5-V n-channel large array MOSFET has been investigated in a 0.15-mu m bipolar-CMOS-DMOS process. Experimental results showed that the secondary breakdown current (It2) is improved by 5 times, and a significant improvement is also observed in the E-SOA and the T-SOA boundary as compared to the original device. In addition, the impact of inserting additional layout pick-ups into the multiple-finger layout of large array MOSFET to the E-SOA, It2, and trigger voltage is also practically investigated in silicon for the LAD with a total width of 12000 mu m.
Semiself-Protection Scheme for Gigahertz High-Frequency Output ESD Protection
(2011-07-01)
Lee, Jian-Hsing
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Huang, Shao-Chang
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Su, Hung-Der
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Chen, Ke-Horng
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電控工程研究所
In this paper, a semiself-protection scheme is proposed and developed for gigahertz output electrostatic-discharge (ESD) protection. The output transistor acts as a trigger device to trigger the ESD protection device, and then, it is turned off when the ESD protection device turns on. Thus, the capacitance of a gigahertz high-frequency output pad can be minimized because this scheme is without any additional trigger device or any passive component.
Two-stage trigger silicon-controller rectifier (SCR) for radio-frequency (RF) input and output protections in nanometer technologies
(2012-08-01)
Lee, Jian-Hsing
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Wu, Yi-Hsun
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Huang, Shao-Chang
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Lee, Yu-Huei
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Chen, Ke-Horng
In this paper, a two-stage trigger (TST) scheme is proposed to implement a low-capacitance and zero-ohm input resistance electrostatic-discharge (ESD) protection device for nanometer technology applications. Besides the main trigger device diode string, the output transistor can also be used as the trigger device. The dimension of the main trigger device can be reduced for minimizing its capacitance with the additional trigger device. Moreover, the output transistor can be as the driving device without any series resistor. This is because the diode string can help to prevent integrated circuits (ICs) from ESD damage before the primary ESD protection device turns on. (c) 2012 Elsevier Ltd. All rights reserved.