Browsing by Author "Lee, Joseph Ya-Min"

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Advance in next Century nanoCMOSFET research
(2007-10-31)
Hwang, Huey-Liang
;
Chiou, Yan-Kai
;
Chang, Che-Hao
;
Wang, Chen-Chan
;
Lee, Kun-Yu
It is well known that Taiwan's IC industry is in the very leading front of the world, and production of 65 nm devices was launched in 2006. Within a few years, the need of high-k dielectrics and metal gates is eminent and truly indispensable. Professor H.L. Hwang (the author) organized 12 professors and 50 graduate students of National Tsing Hua University and Chiao Tung University, and executed this particular project, which is sponsored by the Ministry of Economic Affairs of Republic of China, and is aimed at treating efficiently this problem and transferred the critical technologies to industry in a time frame of 3 years. (C) 2007 Elsevier B.V. All rights reserved.
The Dependence of the Performance of Strained NMOSFETs on Channel Width
(2009-11-01)
Yeh, Lingyen
;
Liao, Ming Han
;
Chen, Chun Heng
;
Wu, Jun
;
Lee, Joseph Ya-Min
The dependence of the performance of strained NMOSFETs on channel width was investigated. When the channel width was varied, the stress in the channel varied accordingly. This changed the electron effective mass and, consequently, the ON-state current I(on). By shrinking the channel width of a strained NMOSFET from 1 to 0.1 mu m and by keeping the channel length at 55 nm, the ON-state drain current per unit channel width was enhanced by 22%. The gate leakage current was also affected by the stress in the channel, which can be explained by the increase in hole barrier height at the Si/SiO(2) interface. Furthermore, when the film stress was increased by 1 GPa, the gate leakage current density J(g) of a strained NMOSFET with a channel width of 0.1 mu m and a length of 55 nm under a negative bias -3 V was reduced by 63%.