Browsing by Author "Lee, Jui-Sheng"

Now showing 1 - 8 of 8

3D DEPTH MAP GENERATION FOR EMBEDDED STEREO APPLICATIONS
(2012)
Lee, Jui-Sheng
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Jian, Guo-An
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Chien, Cheng-An
;
Chen, Peng-Sheng
;
Guo, Jiun-In
This paper presents a low complexity 3D image depth map generation algorithm for embedded stereo applications. The proposed algorithm generates depth information based on a single view 2D image automatically. Owing to different scene characteristics of image, we propose a mechanism to classify images to "Scenery", "Normal" and "Close-up" types first and generate the associated depth map according to the proposed techniques. In addition, we propose a human detection method for strengthening the depth information in images with humans and post-processing for refining depth map. With good quality in the generated depth map, the proposed algorithm achieves about 93% in complexity reduction as compared to the traditional algorithm, which is suitable for realization in both the hardware and embedded systems for portable stereo applications.
A Low Complexity Multi-view Video Encoder Exploiting B-frame Characteristics
(2013)
Miao, Yuan-Hsiang
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Jian, Guo-An
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Wang, Li-Ching
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Lee, Jui-Sheng
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Guo, Jiun-In
This paper proposes a low complexity multi-view video encoder which includes mode decision and early termination based on B-frame characteristics. According to the statistics of coding mode distribution in different B-frame types, we classify all the coding modes into several classes and propose an early terminated mode decision algorithm that can largely reduce the computing complexity. On the other hand, MVD-based adaptive search range scheme is also included in the proposed encoding strategy. In our experimental results, the encoding time is saved up to 91%-93% but the quality loss is controlled within 0.1 dB PSNR drop.
A REAL-TIME PARALLEL SCALABLE VIDEO ENCODER FOR MULTIMEDIA STREAMING SYSTEMS
(2013)
Jian, Guo-An
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Lee, Jui-Sheng
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Tan, Kheng-Joo
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Chen, Peng-Sheng
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Guo, Jiun-In
Scalable video coding (SVC) is a video coding technique that mainly aims its target in resolving problems of multimedia communication between servers and various clients with different computational power, transmission bandwidths, and display resolutions. In this paper, we developed a parallel SVC encoding system to achieve the real-time coding performance of SVC. First, a GOP-level bit-stream structure that is fully compatible with the standard SVC decoder was proposed to eliminate the data dependencies of encoding among GOPs. Based on this bit-stream structure, we developed a parallel SVC encoding algorithm to exploit the parallelism on multicore systems. Finally, the proposed parallel SVC encoder was implemented and integrated into a multimedia streaming system for the evaluation. The experimental results showed that for CIF/QCIF and VGA/QVGA 2-layer SVC encoding, the proposed parallel SVC encoder can achieve 50.96 and 103.99 times speedup with negligible PSNR drop, respectively.
A VIEW SCALABLE MULTI-VIEW VIDEO DECODER SYSTEM
(2013-01-01)
Lee, Jui-Sheng
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Miao, Yuan-Hsiang
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Chien, Cheng-An
;
Chang, Hsiu-Cheng
;
Guo, Jiun-In
This paper presents a view scalable multi-view video decoder system that integrates multiple decoder cores into the proposed system to decode multi-view video and achieve parallel decoding with high view scalability. We manage the firmware for video bit-stream partition and design an arbitration mechanism to balance the work load among decoder cores with a 4KB two-level cache architecture for inter-view/inter-frame prediction data reusing. With such a flexible architecture, the proposed system can reach 1.8 times performance improvement with two decoding cores and 3.5 times with four decoding cores. Based on the proposed system, users only need to adjust the number of decoder cores and set the firmware parameters for different system applications. This feature also benefits to adopting 3D IC packaging or implementation to exploit high bandwidth DRAM access. The proposed view scalable multi-view video decoder system is able to decode multiple-view HD video in real time.
A VIEW SCALABLE MULTI-VIEW VIDEO DECODER SYSTEM
(2013)
Lee, Jui-Sheng
;
Miao, Yuan-Hsiang
;
Chien, Cheng-An
;
Chang, Hsiu-Cheng
;
Guo, Jiun-In
This paper presents a view scalable multi-view video decoder system that integrates multiple decoder cores into the proposed system to decode multi-view video and achieve parallel decoding with high view scalability. We manage the firmware for video bit-stream partition and design an arbitration mechanism to balance the work load among decoder cores with a 4KB two-level cache architecture for inter-view/inter-frame prediction data reusing. With such a flexible architecture, the proposed system can reach 1.8 times performance improvement with two decoding cores and 3.5 times with four decoding cores. Based on the proposed system, users only need to adjust the number of decoder cores and set the firmware parameters for different system applications. This feature also benefits to adopting 3D IC packaging or implementation to exploit high bandwidth DRAM access. The proposed view scalable multi-view video decoder system is able to decode multiple-view HD video in real time.
An AdaBoost Object Detection Design for Heterogeneous Computing with OpenCL
(2015)
Cheng, Bing-Yang
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Lee, Jui-Sheng
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Guo, Jiun-In
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交大名義發表
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National Chiao Tung University
AdaBoost classification with Haar-like features [1] is commonly adopted for object detection. Feature calculation in AdaBoost algorithm is the most time-consuming part, which occupies over 98% of the computation and cannot reach real-time processing with CPU computing only. In this paper we propose an object detection design for heterogeneous computing with OpenCL. By adopting the techniques of scale parallelizing, stage partitioning, and dynamic stage scheduling on AdaBoost algorithm, the proposed design solves load-unbalanced problems when realize in multicore CPU and GPU platform. The proposed object detection design achieves 32.5 fps at D1 resolution on an AMD A10-7850K processor.
An Adaboost-based Two-level Moving Object Detection Architecture with Dynamic ROI Allocation
(2014-01-01)
Lee, Jui-Sheng
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Chang, Hsiu-Cheng
;
Guo, Jiun-In
;
交大名義發表
;
National Chiao Tung University
This paper presents a hardware architecture to detect moving objects based on Adaboost algorithm [1] with Haar-like feature for driving safety. According to the complex appearances of pedestrians and motorcyclists at closer distance, the proposed design supports 12-level scaling for detection window size with dynamic ROI allocation. The stride mode results in highly complex 12-level window size scaling. So a two-level fast search method for decreasing hardware cost while preserving 93.6% detection rate is proposed. The proposed design comprises of 173K gates and 35.7Kbytes SRAM. The maximum working frequency is 200MHz that is able to process VGA@31fps and QVGA@107fps input video. With the detection window sizes scaled from 14x28 to 40x80, the proposed design supports detection at a distance as far as 40 meters.
An Inter-frame/Inter-view Cache Architecture Design for Multi-view Video Decoders
(2012)
Lee, Jui-Sheng
;
Wang, Sheng-Han
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Chou, Chih-Tai
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Chien, Cheng-An
;
Chang, Hsiu-Cheng
In this paper we propose a low-bandwidth two-level inter-frame/ inter-view cache architecture for a view scalable multi-view video decoder, which adopts two decoder cores to decode multi-view videos in parallel. The first level L1 cache is developed for the single video decoder core, which is able to reduce 60% bandwidth in doing inter-frame prediction in average. Moreover, we develop the second level L2 cache architecture to reuse the same reference data for doing interview prediction among different decoder cores, which can further reduce 35% bandwidth. By adopting the proposed two-level cache architecture for doing inter-frame/ inter-view prediction, we can reduce 80% bandwidth through a view scalable multi-view video decoder implementation, which achieves real-time HD1080 dual-view video decoding.