Browsing by Author "Lee, KB"

Now showing 1 - 13 of 13

A bandwidth and memory efficient MPEG-4 shape encoder
(2004)
Lee, KB
;
Chang, NYC
;
Chin, HY
;
Hsu, HC
;
Jen, CW
We have developed a shape encoder hardware for MPEG-4 video coding. On the one hand, the alpha component is compressed and therefore, the size and memory access of alpha frame memory can be reduced to 50% and 56.25% respectively. On the other hand, an efficient data transfer scheme combining the run length coding and addressing mode can reduce average data transfer time to 9.39% and accelerate the shape encoding process. The shape encoder can support MPEG-4 Main Profile at Level 4 in real-time. In addition, verification and testing methods are also considered.
A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization
(2004)
Lee, KB
;
Hsu, HC
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an efficient VLSI architecture of shape-adaptive discrete cosine transform (SA-DCT) for MPEG-4. The proposed architecture contains a cost-effective 1-D variable-length DCT engine and an auto-aligned transpose memory organization. Compared to other designs for SA-DCT, our architecture requires fewer multipliers whereas has higher throughout. Together with address generators and address pointers, the auto-aligned transpose memory organization can achieve transposing, shifting and aligning simultaneously without saving shape information. When clocking at 66.7 MHz, the proposed architecture has a throughput of 43.83 Mpixels/sec.
A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding
(2004)
Lee, KB
;
Lin, JY
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
MPEG-4 shape coding comprises context-based arithmetic encoding (CAE) as its centerpiece. Since the CAE algorithm has complicated coding procedure and strong data dependency, it is hard to exploit its pipeline and parallel facilities. This paper presents a fast dual symbol CAE that runs at a higher clock rate whereas requires less clock cycle count for encoding. The proposed design is based on the unique characteristics of shape information as well as the numerical properties of the probabilities indexed by the contexts, and it is capable of encoding either a singe symbol or two symbols within each clock cycle. Together with the adaptive predication for the order of coding process, redundant operations can be skipped and therefore the average clock cycles for each coding process is improved by a factor of 1.72. Furthermore, the probability table is rearranged to reduce critical path delay. When synthesized from Verilog RTL design by using TSMC 0.35mum 1P4M CMOS technology, the design with I/O pads occupies an area of 2528 x 2520 mum(2) and is capable of running at 100 MHz.
A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding
(2005-02-01)
Lee, KB
;
Lin, JY
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
MPEG-4 shape coding comprises context-based arithmetic encoding (CAE) as its centerpiece. Since the CAE algorithm has a complicated coding procedure and strong data dependency, it is hard to exploit its pipeline and parallel facilities. Furthermore, to encode multiple symbols within one, clock cycle, it needs to overcome the issues of extracting multiple contexts of these symbols, deriving multiple probabilities from these contexts, and performing multiple multiplicative range update operations. This paper presents an efficient pipelined multisymbol CAE architecture for real-time MPEG-4 shape encoding. The proposed design is based on the inherent characteristics of binary alpha blocks as well as the numerical properties of the probabilities indexed;by the contexts, and it is capable of encoding either a singe symbol, or multiple symbols within each clock cycle. To overcome the aforementioned issues under the consideration of the hardware cost and the critical path delay, only symbols with a particular set of contexts are chosen to be processed simultaneously within the same clock cycle. Theoretical analysis shows that the majority of symbols have contexts belonging to this particular set, and therefore CAE processing can be significantly accelerated. An example VLSI implementation of proposed architecture that encodes two symbols within each clock cycle without sacrificing the clock rate can achieve a speedup of 1.47 in comparison with traditional CAE architectures. This particular two-symbol design can support MPEG-4 Main Profile at levels 3 and 4 under extreme and typical conditions, respectively. When synthesized from Verilog RTL design by using TSMC 0.35-mum 1P4M CMOS technology, the design can run at 90 MHz.
An efficient quality-aware memory controller for multimedia platform SoC
(2005-05-01)
Lee, KB
;
Lin, TC
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The ongoing advancements in VLSI technology allow system-on-a-chip (SoC) design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient multilayer, quality-aware memory controller that contains well-partitioned functionality layers to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Layer 0, also called memory interface socket, is a configurable, programmable, and high-efficient SDRAM controller for designers to rapidly integrate SDRAM subsystem into their designs. Together with Layer 1 quality-aware scheduler, the memory controller also has the capability to provide quality-of-service guarantees including minimum access latencies and fine-grained bandwidth allocation for heterogeneous control and computing functional units in SoC designs. Moreover, Layer 2 built-in address generator designed for multimedia processing units can effectively reduce the address bus traffic and therefore further increase the efficiency of on-chip communication. Experimental results of a digital set-top-box emulation system show that the access latency of the latency-sensitive data flows can be effectively reduced by 37%-65% and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.
Design and implementation of a scalable fast Fourier transform core
(2002)
Sung, CH
;
Lee, KB
;
Jen, CW
;
電機學院
;
College of Electrical and Computer Engineering
A novel approach for scalable length Fast Fourier Transform (FFT) in single Processing Element (single PE) architecture has been developed. Scalable length FFT design meets the different lengths requirement of FFT operation in OFDM system [1]. An efficient mechanism that named Interleaved Rotated Data Allocation (IRDA) to replace multiple-port memory with single-port memory has also been proposed. Using single-port memory instead of multiple-port memory makes more area efficient.
High-speed memory-saving architecture for the embedded block coding in JPEG2000
(2002)
Hsiao, YT
;
Lin, HD
;
Lee, KB
;
Jen, CW
;
電子工程學系及電子研究所
This paper presents a high-speed, memory-saving architecture for the embedded block coding algorithm in JPEG2000. The architecture is based on the proposed memory-saving algorithm that can achieve 4K bits reduction in the memory requirement (20% less than conventional approaches) without degrading the delay of the critical path. By exploiting the characteristic that the input symbols of the arithmetic coder in JPEG200 have highly skewed distribution, a simple renormalization strategy is adopted for the code-string register in our pipelined MQ Coder design to enhance the clock rate. The overall design is fully implemented in a chip using TSMC 0.35mum CMOS technology. The chip can operate up to 142 MHz at post-layout simulation and is capable of many applications.
Optimal data transfer and buffering schemes for JPEG 2000 encoder
(2003)
Chiu, MY
;
Lee, KB
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents optimal data transfer and buffering schemes for JPEG 2000 encoder. The data transfer scheme combines bit-level zero run-length coding and addressing mode to reduce data transfer time between Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimized Truncation (EBCOT) to 21%. Furthermore, this data transfer scheme also helps in word-to-bitplane data format conversion from DWT to EBCOT. On the other hand, by jointly considering coding flow of both lifting-based DWT and EBCOT with different design parameters, the reduction in total buffer requirement for both DWT and EBCOT can up to a factor of 4.22.
Optimal frame memory and data transfer scheme for MPEG-4 shape coding
(2004-02-01)
Lee, KB
;
Chin, HY
;
Chang, NYC
;
Hsu, HC
;
Jen, CW
An optimal frame memory and data transfer scheme is proposed for MPEG-4 shape coding in embedded systems. The proposed alpha frame buffer scheme contains two approaches. First, a distributed tile-based memory organization is used to efficiently support the time-varying size of alpha plane. Second, a compression scheme is used to reduce the number of memory access to and the size of the alpha frame memory. Under the criteria of MPEG-4 standard, the size of alpha frame memory can be reduced to 50% by introducing a small index table (2.73%-5.08% of the original frame memory size). A coarse assessment shows that the number of memory reference can be reduced to 56.25%. On the other hand, the proposed data transfer scheme combines the run length coding and addressing mode to reduce average data transfer time to 9.39%. Therefore, the shared system bus can be kept as free as possible, which in turn leads to increasing the potentialities of improvement on system performance. Furthermore, this data transfer scheme also helps in accelerating the processing of shape coding(1).
Optimal frame memory and data transfer scheme for MPEG-4 shape coding
(2003)
Lee, KB
;
Chang, NYC
;
Chin, HY
;
Hsu, HJ
;
Jen, CW
An optimal frame memory and data transfer scheme is proposed for MPEG-4 shape coding in embedded system. Based on the inherent property of shape information, the binary alpha blocks are losslessly compressed with a fixed 50% compression ratio and can be randomly accessed. Therefore the size of frame memory can be reduced to 50% with a small index table (2.73% similar to 5.08% of the original frame memory size), and the number of memory reference can be reduced to 56.25%. The data transfer scheme combines the run length coding and addressing mode to reduce data transfer time to 9.39%.
QME: An efficient subsampling-based block matching algorithm for motion estimation
(2004)
Lee, KB
;
Chin, HY
;
Hsu, HC
;
Jen, CW
;
電子工程學系及電子研究所
This paper presents a new pel subsampling-based search algorithm for motion estimation. The proposed quartet-pel motion estimation (QME) search algorithm reduces the number of pels taken into account for the cost function of the matching criteria at every search position, therefore reduces the computational complexity and the required memory bandwidth. Furthermore, the proposed algorithm has a regular data flow, which in turn leads to hardware-efficient implementations. Simulation results show that QME achieves almost the same coding performance as full-search block matching algorithm (FBMA) in terms of PSNR and the size of the coded bitstream. A flexible and efficient architecture design using QME is also proposed. The flexibility is based on the configurations of processing units, such that the processing time and memory access of QME architecture can be reduced with facility. On the other hand, the efficiency of proposed hardware design, characterized by normalized processing capability per gate, also surpasses other designs.
Quality-aware memory controller for multimedia platform SOC
(2003)
Lin, TC
;
Lee, KB
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The ongoing advancements in VLSI technology allow SoC design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient memory controller that contains a quality-aware scheduler and a configurable DRAM memory interface socket to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Simulation results show that the latency of the latency-sensitive data flow can be reduced to 50%, and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.
Trace-path analysis and performance estimation for multimedia application in embedded system
(2004)
Chang, NYC
;
Lee, KB
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-level performance estimation can help assess the performance in the early development stage of embedded system with real-time constraint efficiently; however the estimation accuracy has long been an issue. In this paper, a performance estimation method called trace-path analysis based on high-level execution path tracing analysis which takes the effect of multiple execution paths into consideration is proposed. Multiple execution path resolutions and a linear model for non-deterministic node cost are incorporated to yield better estimation accuracy. The estimation of error is also covered in this context so that the degree of the estimation accuracy can be known. Experiments taking MPEG-4 shape coding as an example shows that the proposed approach can achieve an average of 1.88% estimation error per QCIF frame, which is better than the 12.38% of the bitstream analysis approach.