Browsing by Author "Lee, Kao-Chi"

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A Model-Based-Random-Forest Framework for Predicting V-t Mean and Variance Based on Parallel I-d Measurement
(2018-10-01)
Lin, Chien-Hsueh
;
Tsai, Chih-Ying
;
Lee, Kao-Chi
;
Yu, Sung-Chu
;
Liau, Wen-Rong
To measure the variation of device V-t requires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of V-t for a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of V-t based only on the combined I-d measured from parallel connected DUTs. The proposed framework can further minimize the total number of I-d measurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R -squared for predicting either V-t mean or V-t variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a 120.3x speedup on overall test time for test structures with 800 DUTs.
Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators
(2017-01-01)
Lee, Kao-Chi
;
Wu, Kai-Chiang
;
Tsai, Chih-Ying
;
Chao, Mango Chia-Tso
;
資訊工程學系
As the technology of IC manufacturing continually scales down, process variations become more and more crucial than before. To statistically characterize local process variations, the traditional array-based test structure measures threshold voltage (Vt) for a sufficiently large number of devices-undertest (DUTs). However, the array-based test structure requires long time for DUT-by-DUT measurement; furthermore, it suffers from significant IR drop or leakage current due to the large number of DUTs, which results in the loss of measurement accuracy. In this paper, we present a novel sense-amplifierbased test structure that can monitor process variations based on rapid characterization of Vt variance, with marginal error of accuracy. A test-chip containing 120 NMOS and 120 PMOS DUTs has been implemented in 28nm CMOS process technology. Various experiments reveal promising efficiency and accuracy of the proposed test structure, for characterizing Vt variance.
Predicting V-t Mean and Variance from Parallel I-d Measurement with Model-Fitting Technique
(2016)
Tsai, Chih-Ying
;
Lee, Kao-Chi
;
Lin, Chien-Hsueh
;
Yu, Sung-Chu
;
Liau, Wen-Rong
To measure the variation of device V-t requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of V-t for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of V-t based on only the combined I-d measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of V-t mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of I-d measurement per DUT.