Browsing by Author "Lee, Kuen-Di"

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A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
(2015-05-01)
Lu, Chien-Yu
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Chuang, Ching-Te
;
Jou, Shyh-Jye
;
Tu, Ming-Hsien
;
Wu, Ya-Ping
This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V-DD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 degrees C. At 0.325 V and 25 degrees C, the chip operates at 600 kHz with 5.78 mu W total power and 4.69 mu W leakage power, offering 2x frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 degrees C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
(2012-12-01)
Lu, Chien-Yu
;
Tu, Ming-Hsien
;
Yang, Hao-I
;
Wu, Ya-Ping
;
Huang, Huan-Shun
This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 x 385 mu m(2) 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 degrees C. The measured total power consumption is 3.94 mu W at 0.33 V, 500 kHz, and 25 degrees C.
A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
(2016-05)
Wu, Shang-Lin
;
Lu, Chien-Yu
;
Tu, Ming-Hsien
;
Huang, Huan-Shun
;
Lee, Kuen-Di
This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tristate pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128 kb SRAM macro implemented in 40 nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with V-DD down to 0.35 V (similar to 100 mV lower than the threshold voltage). Data is held down to 0.325 V with 2.53 mu W standby power. The measured maximum operation frequency is 375 kHz with total power consumption 5.43 mu W at 0.35 V. (C) 2016 Elsevier Ltd. All rights reserved.
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
(2017-07-01)
Wu, Shang-Lin
;
Li, Kuang-Yu
;
Huang, Po-Tsang
;
Hwang, Wei
;
Tu, Ming-Hsien
This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron).
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
(2013)
Chang, Chi-Shin
;
Yang, Hao-I
;
Liao, Wei-Nan
;
Lin, Yi-Wei
;
Lien, Nan-Chun
We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25 degrees C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25 degrees C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25 degrees C.
A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
(2011)
Yang, Hao-I
;
Yang, Shih-Chi
;
Hsia, Mao-Chih
;
Lin, Yung-Wei
;
Lin, Yi-Wei
This paper describes a high-performance low V(MIN) SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V(MIN). A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
(2012-06-01)
Tu, Ming-Hsien
;
Lin, Jihi-Yu
;
Tsai, Ming-Chien
;
Lu, Chien-Yu
;
Lin, Yuh-Jiun
This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-inter-leaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V-DD down to 0.35 V (similar to 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 mu W power. Data is held down to 0.275 V with 2.29 mu W Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V-DD around/above 1.0 V.
An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array
(2012)
Lin, Geng-Cing
;
Wang, Shao-Cheng
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Lin, Yi-Wei
;
Tsai, Ming-Chien
;
Chuang, Ching-Te
We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85 degrees C to -45 degrees C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.
Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM
(2012)
Wang, Shao-Cheng
;
Lin, Geng-Cing
;
Lin, Yi-Wei
;
Tsai, Ming-Chien
;
Chiu, Yi-Wei
We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps similar to 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 similar to 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
(2012)
Yang, Hao-I
;
Lin, Yi-Wei
;
Hsia, Mao-Chih
;
Lin, Geng-Cing
;
Chang, Chi-Shin
This paper presents a 1.0Mb high-performance 0.6V V-MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is 1.517GHz@1.5V and 469MHz@0.7V.