Browsing by Author "Lee, Kuo-Fu"

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3D Device Simulation of Work Function and Interface Trap Fluctuations on High-kappa/Metal Gate Devices
(2010)
Cheng, Hui-Wen
;
Li, Fu-Hai
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Han, Ming-Hung
;
Yiu, Chun-Yen
;
Yu, Chia-Hui
This work, for the first time, examines the work function fluctuation (WKF) and interface trap fluctuation (ITF) using experimentally calibrated 3D device simulation on high-kappa / metal gate technology. The random WKs result in 36.7 mV threshold voltage fluctuation (sigma V(th)) for 16 nm N-MOSFETs with TiN gate, which is rather different from the result of averaged WKF (AWKF) method [1] due to localized random WK effect. The ITF affects the subthreshold region (the normalized sigma I(D) > 48%) and is suppressed for devices under strong inversion. Estimation of statistical covariance confirms the dependence of IT on the metal gate's WK; thus, the impacts of WKF and ITF on device and circuit variability should be considered together properly. Such variability induced static noise margin fluctuation of SRAM exceeds the influence of random dopants and cannot be ignored.
Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants
(2010-04-01)
Lee, Kuo-Fu
;
Li, Yiming
;
Hwang, Chih-Hong
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傳播研究所
;
電機工程學系
Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.
Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants
(2010-04-01)
Lee, Kuo-Fu
;
Li, Yiming
;
Hwang, Chih-Hong
;
電子工程學系及電子研究所
;
電信工程研究所
Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.
Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell
(2010-05-01)
Lee, Kuo-Fu
;
Li, Yiming
;
Li, Tien-Yen
;
Su, Zhong-Cheng
;
Hwang, Chin-Hong
In this study, a three-dimensional "atomistic" coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM (sigma(SNM)) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the sigma(SNM) is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era. (C) 2010 Elsevier Ltd. All rights reserved.
Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal-Oxide-Semiconductor Field-Effect-Transistor Devices
(2011-04-01)
Li, Yiming
;
Lee, Kuo-Fu
;
Yiu, Chun-Yen
;
Chiu, Yung-Yueh
;
Chang, Ru-Wei
In this work, we explore for the first time dual-material gate (DMG) and inverse DMG devices for suppressing the random-dopant (RD)-induced characteristic fluctuation in 16 nm metal-oxide-semiconductor field-effect-transistor (MOSFET) devices. The physical mechanism of suppressing the characteristic fluctuation of DMG devices is observed and discussed. The achieved improvement in suppressing the RD-induced threshold voltage, on-state current, and off-state current fluctuations are 28, 12.3, and 59%, respectively. To further suppress the fluctuations, an approach that combines the DMG method and channel-doping-profile engineering is also advanced and explored. The results of our study show that among the suppression techniques, the use of the DMG device with an inverse lateral asymmetric channel-doping-profile has good immunity to fluctuation. (C) 2011 The Japan Society of Applied Physics
Dynamic Characteristic Optimization of 14 a-Si:H TFTs Gate Driver Circuit Using Evolutionary Methodology for Display Panel Manufacturing
(2011-05-01)
Li, Yiming
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Lee, Kuo-Fu
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Lo, I-Hsiu
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Chiang, Chien-Hshueh
;
Huang, Kuen-Yu
For thin-film transistor liquid crystal display (TFT-LCD) panel manufacturing, a gate driver circuit with amorphous silicon TFT plays an important role. In this paper, an amorphous silicon gate (ASG) driver circuit is optimized to improve circuit's dynamic characteristics. The adopted simulation-based evolutionary method integrates genetic algorithm and circuit simulator on the unified optimization framework. The circuit consisting of 14 hydrogenated amorphous silicon TFTs (a-Si: H TFTs) used in a large panel is optimized for the given specifications of the rise time < 1.5 mu s, the fall time < 1.5 mu s, and the ripple voltage < 3 V with minimizing the total layout area. By optimizing the width and passive components of the 14 devices, the results of this study successfully meet the desired specifications, where the sensitivity analysis is further conducted to verify the characteristic variation with respect to the optimized parameters. To validate the results, the optimized circuit is fabricated with 4-mu m a-Si: H TFT process, and the experimental result confirms the practicability of achieved design. The ripple voltage within 2.0 V is successfully obtained while the rise and fall times satisfy the required specifications for the fabricated sample. A 35% reduction of the optimized total devices width of a-Si: H TFTs is achieved.
Hybrid Genetic Algorithm with Mixed Mutation Mechanism for Optimal Display Panel Circuit Design
(2010-01-01)
Lo, I-Hsiu
;
Li, Yiming
;
Lee, Kuo-Fu
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, a hybrid genetic algorithm which combines crossover operator of conventional genetic algorithm (GA) and mixed mutation mechanisms is proposed for the design and optimization of the panel gate driver circuits with amorphous silicon thin-film transistor (ASG driver circuit). The shooting local search method is applied on the first half of sorted population while the mutation of differential evolution (DE) is applied on the others after the end of crossover. This mechanism can accelerate the speed of convergence and keep the diversity in the meanwhile. For sizing of topology -given ASG driver circuits, the system which integrates proposed algorithm and circuit simulator to optimize crucial characteristics with practical constraints is implemented and tested. The results indicate that the proposed algorithm is effective and efficient, compared with conventional GA.
Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits
(2009)
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Han, Ming-Hung
;
Lee, Kuo-Fu
;
Cheng, Hui-Wen
This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.