Browsing by Author "Lee, Ming-Hsiu"

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A Comprehensive Study of 3-stage High Resistance State Retention Behavior for TMO ReRAMs from Single Cells to a Large Array
(2017-01-01)
Lin, Yu-Hsuan
;
Ho, Yung-Han
;
Lee, Ming-Hsiu
;
Wang, Chao-Hung
;
Lin, Yu-Yu
For the first time the retention of high resistance state (HRS) in resistive random access memory (ReRAM) is found to compose of three stages - extending tail-bits, distribution shift, and then distribution broadening. This work provides a comprehensive study on the HRS's retention behavior in WOx-based ReRAMs from single device characteristics to group distribution. Different from conventional activation energy (Ea) analysis, the mean and variance of the array distribution are presented to overcome the non-uniform Ea issue. Since the extracted Ea fits well with Vo(2+) (oxygen vacancy) migration characteristics, the three retention stages are suggested to be the competing results from the migration, recombination, and generation of the Vo(2+) and O2- in the gap region. A three-dimensional retention model with kinetic Monte Carlo simulator and trap-assisted tunneling conduction is proposed to discuss the dominating mechanism in different time and temperature scales. The mechanism for random telegraph noise is also included to illustrate the fluctuating nature of the HRS cells.
A Novel Varying-Bias Read Scheme for MLC and Wide Temperature Range TMO ReRAM
(2016-11)
Lin, Yu-Hsuan
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Lee, Ming-Hsiu
;
Wu, Jau-Yi
;
Lin, Yu-Yu
;
Lee, Feng-Ming
Resistance of transition metal oxide (TMO) resistive random access memory (ReRAM) depends sharply on temperature, resulting in drastic memory window loss at high temperature. Thus, it is difficult to design the ReRAM that can serve a wide range of operating conditions. It is especially challenging to achieve multi-level-cell (MLC) ReRAM because of the large temperature dependency. This letter investigates both the temperature and read bias dependencies of WOx ReRAM, and found both can be well understood by a modified space-charge limited conduction model. Using this model, we have designed a novel read scheme that varies the read bias according to the device temperature and compensates for the temperature effect on cell resistance. Since TMO ReRAM devices depend on defect states, cell-to-cell and cycle-to-cycle variations are naturally large. An algorithm is designed to address the variability. A 1-Mb WOx ReRAM array is fabricated to both characterize the bias and temperature dependencies and verify the new read scheme. A large and constant memory window is preserved for MLC across a wide temperature range (-40 degrees C-125 degrees C), suitable for high-reliability applications.
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications
(2017-01)
Khwa, Win-San
;
Chang, Meng-Fan
;
Wu, Jau-Yi
;
Lee, Ming-Hsiu
;
Su, Tzu-Hsiang
For multilevel cell (MLC) phase change memory (PCM), resistance drift ( R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100x, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications
(2017-01)
Khwa, Win-San
;
Chang, Meng-Fan
;
Wu, Jau-Yi
;
Lee, Ming-Hsiu
;
Su, Tzu-Hsiang
For multilevel cell (MLC) phase change memory (PCM), resistance drift ( R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100x, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles.
A Resistance-Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage-Class Memory Applications
(2016)
Khwa, Win-San
;
Chang, Meng-Fan
;
Wu, Jau-Yi
;
Lee, Ming-Hsiu
;
Su, Tzu-Hsiang
Excellent High Temperature Retention of TiOXNV ReRAM by Interfacial Layer Engineering
(2018-01-01)
Lin, Yu-Hsuan
;
Lee, Dai-Ying
;
Wang, Chao-Hung
;
Lee, Ming-Hsiu
;
Ho, Yung-Han
Since the resistance switching of the transition metal oxide (TMO) resistive random access memory (ReRAM) is based on thc interaction between the oxygen ions and vacancies, the unintentional oxygen/vacancy reaction should be avoided during data retention. This work demonstrates significant improvements on the retention performance by inserting a Si layer in the TiO Ny ReRAM to block the diffusion of oxygen ions through the Ti/TiO,N interface. The mechanism and factors that influenced thc IIRS and LRS retention arc also studied. The retention performance of HRS is correlated with its RESET level while the LRS retention depends on the programming current. The proposed Ti/Si/TiO,N, ReRAMs can switch for more than 103 cycles from array testing results.
Excellent Resistance Variability Control of WOx ReRAM by a Smart Writing Algorithm
(2016)
Lin, Yu-Hsuan
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Wu, Jau-Yi
;
Lee, Ming-Hsiu
;
Wang, Tien-Yen
;
Lin, Yu-Yu
TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.
Performance Impacts of Analog ReRAM Non-ideality on Neuromorphic Computing
(2019-03-01)
Lin, Yu-Hsuan
;
Wang, Chao-Hung
;
Lee, Ming-Hsiu
;
Lee, Dai-Ying
;
Lin, Yu-Yu
Resistive random access memory (ReRAM) is often considered as a strong candidate for storing the weights in non-von Neumann neuromorphic computing systems. This paper studies how nonideal memory characteristics, which include programing error, read fluctuation, and retention, affect the inference accuracy of the analog ReRAM neural networks by incorporating memory characteristics extracted from 1-Mb ReRAM into a simulated inference-only neural network. This paper also shows that the different layer in the network can tolerate different amount of such imperfects. We learned four key points: 1) the conductance range of memory with less relative fluctuation is preferred for designing the weight-conductance mapping; 2) the control of programing error is essential for high inference accuracy; 3) retention-induced conductance drift can be fatal to the neuromorphic system. A compensation scheme is proposed in this paper which can effectively recover the inference accuracy; and 4) for multilayer networks, avoiding weight errors in the front layers can help to maintain the inference accuracy by reducing calculation error which may otherwise accumulate and pass down the networks. The concepts and approaches of this paper can also be applied to evaluate other types of nonvolatile memories for artificial neural networks.