Browsing by Author "Lee, Po-Hao"

Now showing 1 - 2 of 2

A reliability model for low-temperature polycrystalline silicon thin-film transistors
(2007-05-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Lee, Po-Hao
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We proposed here a reliability model that successfully. introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.
Plasma damage-enhanced negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors
(2006-11-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Chen, Wei-g Chen
;
Lin, Hsiao-Yi
;
Yeh, Kuan-Lin
In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in UPS TFTs. That is, when performing the NBTI measurement, the UPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the UPS TFT circuitry design.