Browsing by Author "Lee, Ren-Jie"

Now showing 1 - 9 of 9

A Study of Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow
(2013-03-01)
Lee, Ren-Jie
;
Chen, Hung-Ming
;
交大名義發表
;
National Chiao Tung University
IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this article, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile that combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring.
Area-I/O RDL Routing for Chip-Package Codesign Considering Regional Assignment
(2010-01-01)
Lin, Kun-Sheng
;
Hsu, Hsin-Wu
;
Lee, Ren-Jie
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
Flip-Chip package provides high density I/Os and better performance in package size, signal/power integrety, and wirelength. Routing on its Re-Distribution Layer (RDL) is one of the most difficult stage in Flip-Chip packaging due to the increasing number of I/Os in modern VLSI designs. Area I/O can shorten the signal path and further increases the I/O density, but the design complexity is also higher. The Area I/O RDL routing problem is introduced in this paper, considering wirelength minimization and chip-package codesign. The proposed algorithm effectively solves the problem. 100% routability is guaranteed, from block ports to I/O pads and from I/O pads to bump pads. The authors propose the concept of regional assignment to evaluate the skew between bumps and balls. It leads the nets to route within neighbor sectors rather than the opposite sector. The experimental results, on 7 industrial designs, show that the router greatly minimizes bump-ball skew compared with [12], with reasonable extra wirelength.
Board- and Chip-Aware Package Wire Planning
(2013-08-01)
Lee, Ren-Jie
;
Hsu, Hsin-Wu
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The slow turnaround between design, package, and system houses has been one of the primary concerns in the semiconductor business. There is a serious lag in the development time of the systems due to time-consuming interface design between the chip, package, and board. In order to enable chip-package-board codesign to speed up the design process, we propose an approach to address this issue by efficiently planning wires for board and chip design awareness, which includes the package pin-out designation and the corresponding wire planning in package and board. We model the problem as an interval intersection problem. Because of the special need in pin-out rules, an algorithm to resolve the problem is developed. We then use some optimization techniques to further improve objectives such as global wire congestion and length deviation. Our results show that a very efficient estimation can be made considering those important objectives, and package congestion can be successfully mitigated.
Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign
(2011-05-01)
Lee, Ren-Jie
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In conventional package design, engineers designate the ball grid array (BGA) pin-out manually, this always postpones the time-to-market (TTM) of products due to the turn-around between package and design houses. Recent papers propose a method of automatically generating the pin-out and taking signal integrity (SI), power delivery integrity (PI), and routability (RA) into account simultaneously by pin-block design and floorplanning, thus dramatically speeding up the developing time. However, this approach ignores the considerations of shorter path length and equilength/length matching in routing printed circuit board (PCB) trace and pin-out assignment for high-speed interface IP designs, such as USB and PCI Express. Since these features are the most important performance metrics during chip-package-board codesign, in this paper we propose the ideas to optimize the system interconnects during package pin-out design. These ideas keep the same minimized package size as aforementioned recent work and ensure that SI, PI, and RA can still be considered with significant reduction in design cost. It is achieved by relaxing the restriction of pin-block side and order on the package, usually specified by package designers. The experimental results on industrial chipset design cases show that the average improvement of our pin-block planner is over 40% when comparing the design cost with the previous work, among which we have one case accommodated over a thousand pins. Our ideas also work for any kind of pin-block or pin-group configurations.
Fast flip-chip pin-out designation respin by pin-block design and floorplanning for package-board codesign
(2007)
Lee, Ren-Jie
;
Lai, Ming-Fang
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface design has been a time-consuming process. This paper proposes a novel and efficient approach to designating pinout for flip-chip BGA package when designing chipsets. The proposed approach can not only automate the assignment of more than 200 I/O pins on package, but also precisely evaluate package size which accommodates all pins with almost no void pin positions, as good as the one from manual design. Furthermore, the practical experience and techniques in designing such interface has been accounted for, including signal integrity, power delivery and routability. This efficient pin-out designation and package size estimation by pin-block design and floorplanning provides much faster turn around time, thus enormous improvement in meeting design schedule. The results on two real cases show that our methodology is effective in achieving almost the same dimensions in package size, compared with manual design in weeks, while simultaneously considering critical issues in package-board codesign. To the best of our knowledge, this is the first attempt in solving flip-chip pin-out placement problem in package-board codesign.
Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign
(2009-08-01)
Lee, Ren-Jie
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Deep submicrometer effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface design has been a time-consuming process. This paper proposes a novel and efficient approach to designating pin-out, which is a package ball chart describing pin locations for flip-chip BGA package when designing chipsets. The proposed approach can not only automate the assignment of more than 200 input/output (I/O) pins on package, but also precisely evaluate package size which accommodates all pins with almost no void pin positions, as good as the one from manual design. Furthermore, the practical experience and techniques in designing such interface has been accounted for, including signal integrity, power delivery and routability. This efficient pin-out designation and package size estimation by pin-block design and floorplanning provides much faster turn around time, thus enormous improvement in meeting design schedule. Our pin-block design contains two major parts. First, we have pin-block construction to locate signal pins within a block along the specific patterns. Six pin patterns are proposed as templates which are automatically generated according to the user-defined constraints. Second, we have pin-blocks grouping to group all pin-blocks into package boundaries. Two alternative pin-blocks grouping strategies are provided for various applications such as chipset and field-programmable gate array (FPGA). The results on two real cases show that our methodology is effective in achieving almost the same dimensions in package size, compared with manual design in weeks, while simultaneously considering critical issues and package size migration in package-board codesign.
On Routing Fixed Escaped Boundary Pins for High Speed Boards
(2011-01-01)
Tsai, Tsung-Ying
;
Lee, Ren-Jie
;
Chin, Ching-Yu
;
Kuan, Chung-Yi
;
Chen, Hung-Ming
Routing for high speed boards is still achieved manually nowadays. There have been some related works in escape routing to solve this problem recently, however a more practical problem is not addressed. Usually the pack-ages/components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to follow when the board design starts. Previous works in escape routing are not likely to be used due to this nature, in this work, we describe this fixed ordering boundary pin escaping problem, and propose a practical approach to solve it. Not only can we have a way to address, we also further plan the wires in a better way to preserve the precious routing resources in the limited number of layers on the board, and to effectively deal with obstacles. our approach has different feature compared with conventional shortest-path-based routing paradigm. In addition, we consider length-matching requirement and wire shape resemblance for high speed signal routes on board. Our results show that we can utilize routing resource very carefully, and can account for the resemblance of nets in the presence of the obstacles. Our approach is workable for board busses as well.
Pin-out Designation Method for Package-Board Codesign
(2011-04-21)
Lee, Ren-Jie
;
Chen, Hung-Ming
A pin out designation method for package board codesign having steps of defining pin characteristics and requirements, generating multiple pin patterns, pin blocks construction and grouping and pin blocks floorplanning. Designers may use an EDA tool to generate multiple pin patterns, use the pin patterns to construct multiple pin blocks, group the pin blocks around four sides of a chip and adjusts the pin blocks into a minimized package size of the chip.
Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow
(2011)
Lee, Ren-Jie
;
Chen, Hung-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this paper, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile which combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring.